ak5365 AKM Semiconductor, Inc., ak5365 Datasheet

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ak5365

Manufacturer Part Number
ak5365
Description
24-bit 96khz ?? Adc With Selector/pga/alc
Manufacturer
AKM Semiconductor, Inc.
Datasheet

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Part Number:
ak5365VQ
Manufacturer:
AKM
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20 000
ASAHI KASEI
AK5365 is a high-performance 24-bit, 96kHz sampling ADC for consumer audio and digital recording
applications. Thanks to AKM’s Enhanced Dual-Bit modulator architecture, this analog-to-digital converter
has an impressive dynamic range of 103dB with a high level of integration. The AK5365 has a 5-channel
stereo input selector, an input Programmable Gain Amplifier with an ALC function. All this integration with
high-performance makes the AK5365 well suited for CD and DVD recording systems.
MS0164-E-01
1. 24bit Stereo ADC
2. 3-wire Serial P Interface / I
3. Master / Slave Mode
4. Master Clock : 256fs/384fs/512fs
5. Sampling Rate : 32kHz to 96kHz
6. Power Supply
7. Power Supply Current : 27mA
8. Ta = -40
9. Package : 44pin LQFP
5ch Stereo Inputs Selector
Input PGA from +12dB to 0dB, 0.5dB Step
Auto Level Control (ALC) Circuit
Digital HPF for offset cancellation (fc=1.0Hz@fs=48kHz)
Digital Attenuator
Soft Mute
Single-end Inputs
S/(N+D) : 94dB
DR, S/N : 103dB
Audio I/F Format : 24bit MSB justified, I
AVDD: 4.75
DVDD: 3.0
85 C
5.25V (typ. 3.3V)
5.25V (typ. 5.0V)
24-Bit 96kHz
2
C-Bus
GENERAL DESCRIPTION
FEATURES
- 1 -
ADC with Selector/PGA/ALC
2
S
AK5365
[AK5365]
2002/08

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ak5365 Summary of contents

Page 1

... AK5365 is a high-performance 24-bit, 96kHz sampling ADC for consumer audio and digital recording applications. Thanks to AKM’s Enhanced Dual-Bit modulator architecture, this analog-to-digital converter has an impressive dynamic range of 103dB with a high level of integration. The AK5365 has a 5-channel stereo input selector, an input Programmable Gain Amplifier with an ALC function. All this integration with high-performance makes the AK5365 well suited for CD and DVD recording systems ...

Page 2

... ROUT MS0164-E-01 M/S SEL2 SEL1 SEL0 IPGAL IPGA (ALC) ADC IPGA (ALC) IPGAR SMUTE Block diagram - 2 - PDN ALC CTRL LRCK HPF Audio I/F Controller DATT MCLK SDTO Control Register I/F CSN CCLK CDTI CAD1 SCL SDA [AK5365] AVDD AVSS DVDD DVSS BICK VCOM 2002/08 ...

Page 3

... LIN5 1 TEST1 2 LIN4 3 TEST2 4 LIN3 5 TEST3 6 LIN2 7 TEST4 8 LIN1 9 LOPIN 10 LOUT MS0164-E-01 40 +85 C 44pin LQFP (0.8mm pitch) Evaluation Board for AK5365 AK5365VQ Top View [AK5365 ] 33 CSN/CAD1 32 CCLK/SCL 31 CDTI/SDA 30 SEL2 29 SEL1 28 SEL0 27 SMUTE ...

Page 4

... Digital Power Supply Pin, 3.0 5.25V 21 SDTO O Audio Serial Data Output Pin 22 BICK I/O Audio Serial Data Clock Pin Note: All digital input pins except pull-down pins should not be left floating. Note: TEST1, TEST2, TEST3 and TEST4 pins should be connected to AVSS. MS0164-E-01 PIN/FUNCTION Function - 4 - [AK5365 ] 2002/08 ...

Page 5

... C Control Control & Compatible, “L” : 3-wire Control “L” : Slave Mode - 5 - [AK5365 ] (CTRL pin = “L”) (CTRL pin = “H”) (CTRL pin = “L”) (CTRL pin = “H”) (CTRL pin = “L”) (CTRL pin = “H”) 2002/08 ...

Page 6

... Note 3. The power up sequence between AVDD and DVDD is not critical. WARNING: AKM assumes no responsibility for the usage beyond the conditions in this datasheet. MS0164-E-01 ABSOLUTE MAXIMUM RATINGS Symbol AVDD DVDD (Note 2) GND IIN VINA VIND Ta Tstg Symbol min AVDD 4.75 DVDD 3 [AK5365 ] min max Units 0.3 6.0 V 0 0.3 AVDD+0.3 V 0.3 DVDD+0 ...

Page 7

... Note 11. All digital input pins are held DVDD or DVSS. MS0164-E-01 ANALOG CHARACTERISTICS min 10 (Note (Note 5) 6.3 (Note 6) 0.9 (Note 7) 6.3 0.2 0 9.5 (Note (Note 9) 90 (Note 10) (Note 11) IPGA (Gain : 0dB [AK5365 ] typ max Units 50 k 100 dB 108 1.1 Vrms 0.5 0.8 dB + Bits 94 ...

Page 8

... 21.768 - 22.0 - 24 1.0 2.9 6.5 Symbol min typ 43.536 - 44.0 - 48 [AK5365 ] max Units 21.5 kHz - kHz - kHz - kHz kHz 0.005 max Units 43.0 kHz - kHz - kHz - kHz kHz 0.005 2002/08 ...

Page 9

... S mode) tLRS tBSD fBCK dBCK tMBLR 20 tBSD [AK5365 ] typ Max Units - - V - 30%DVDD 0 0 typ max Units 24.576 MHz kHz 96 kHz ...

Page 10

... Note 17. Data must be held long enough to bridge the 300ns-transition time of SCL. Note 18. The AK5365 can be reset by bringing the PDN pin = “L”. Note 19. This cycle is the number of LRCK rising edges from the PDN pin = “H”. Note 20. This cycle is the number of LRCK rising edges from the PWN bit = “1”. ...

Page 11

... ASAHI KASEI Timing Diagram MCLK tCLKH LRCK BICK tBCKH LRCK tBLR BICK tLRS SDTO MS0164-E-01 1/fCLK tCLKL 1/fs tBCK tBCKL Clock Timing tLRB tBSD Audio Interface Timing (Slave mode [AK5365 ] VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL 50%DVDD 2002/08 ...

Page 12

... CDTI D2 MS0164-E-01 dBCK tBSD Audio Interface Timing (Master mode) tCSS tCCKL tCCKH tCDS C1 C0 WRITE Command Input Timing tCSH D1 D0 WRITE Data Input Timing - 12 - [AK5365 50%DVDD 50%DVDD 50%DVDD VIH VIL VIH VIL tCDH VIH R/W VIL tCSW VIH VIL VIH VIL VIH ...

Page 13

... Stop Start CSN SDTO PDN SDTO PDN MS0164-E-01 tHIGH tF tHD:DAT tSU:DAT tSU:STA Start Bus Mode Timing tPDV tPDV tPD Power Down & Reset Timing - 13 - [AK5365 ] VIH VIL tSP VIH VIL tSU:STO Stop VIH VIL 50%DVDD VIH VIL 50%DVDD VIL 2002/08 ...

Page 14

... AK5365 may draw excess current due to its use of internal dynamically refreshed logic. If the external clocks are not present, place the AK5365 in power-down mode (PDN pin = “L” or PWN bit = “0”). In master mode, the master clock (MCLK) must be provided unless PDN pin = “L”. ...

Page 15

... Master Mode and Slave Mode The M/S pin selects either master or slave mode. M/S pin = “H” selects master mode and “L” selects slave mode. The AK5365 outputs BICK and LRCK in master mode. In slave mode, MCLK, BICK and LRCK are input externally. Digital High Pass Filter The ADC has a digital high pass filter for DC offset cancellation ...

Page 16

... ASAHI KASEI Power-up/down The AK5365 is placed in the power-down mode by bringing PDN pin = “L” and the digital filter is also reset at the same time. This reset should always be done after power-up. An analog initialization cycle starts after exiting the power-down mode. Therefore, the output data SDTO becomes available after 516 cycles of LRCK. ...

Page 17

... Unsettling PDN INITA Unsettling 00H 00H Unsettling “0” MCLK, LRCK, BICK MCLK, BICK, LRCK The clocks can be input. MCLK The clocks can be input. Unsettling Fixed to “L” Figure 4. Power-up Sequence [AK5365 ] Normal 7FH 7FH FI Output MCLK BICK, LRCK 2002/08 ...

Page 18

... ASAHI KASEI Input Selector The AK5365 includes 5ch stereo input selectors (Figure 5). The input selector selector. The input channel is set by the SEL2-0 bits (Table 6) and the SEL2-0 pins (Table 7). The SEL2-0 pins should be fixed to “LLL” if the AK5365 is controlled by the SEL 2-0 bits, because the setting of the SEL2-0 pins are prior to the SEL2-0 bits setting. ...

Page 19

... S compatible and the serial control interface is I Audio Interface Format Serial Control Interface Note 3-wire Control 2 2 24bit Compatible I C-Bus Control Table 8. CTRL pin Function 2 S compatible by DIF bit. When the CTRL 2 S compatible [AK5365 ] (1) LIN 2 /RIN2 2 C-bus control mode. 2002/08 ...

Page 20

... MS0164-E-01 Rf LOPIN LOUT LIN1 LIN2 LIN3 LIN4 Pre-Amp LIN5 RIN1 RIN2 Pre-Amp RIN3 RIN4 RIN5 ROPIN ROUT Rf Figure 7. Input ATT ATT Gain [dB 11. Table 9. Input ATT example - 20 - [AK5365 IPGAL To IPGA To IPGA IPGAR IPGAL/R pin 1.02Vrms 1.02Vrms 1Vrms 2002/08 ] ...

Page 21

... ASAHI KASEI Input Volume The AK5365 includes two independent channel analog volumes (IPGA) with 25 levels at 0.5dB steps located in front of the ADC. The digital volume controls (DATT) have 128 levels (including MUTE) and is located after the ADC. Both the analog and digital volumes are controlled through the same register address. When the MSB of the register is “1”, the IPGA changes and when the MSB = “ ...

Page 22

... ALC operation. [2] ALC Recovery Operation The ALC recovery refers to the amount of time that the AK5365 will allow a signal to exceed a predetermined limiting value prior to enabling the limiting function. The ALC recovery operation uses the WTM1-0 bits to define the wait period used after completing an ALC limiter operation. If the input signal does not exceed the “ALC Recovery Waiting Counter Reset Level” ...

Page 23

... Figure 8. ALC Level diagram example (ALC=OFF) In Figure 9, Input ATT is 6dB. Input 2Vrms 1Vrms 0.5Vrms Figure 9. ALC Level diagram example (ALC=OFF) MS0164-E-01 ATT IPGA ADC -12dB -12dB +6dB +12dB ATT IPGA ADC -6dB -6dB -6dB +6dB -6dB +12dB - 23 - [AK5365 ] 0dBFS 0dBFS 2002/08 ...

Page 24

... Input 2Vrms 1Vrms 0.5Vrms 0.25Vrms Figure 11. ALC Level diagram example (ALC=ON) MS0164-E-01 ATT ALC ADC -12dB -12dB -0.5dB +5.5dB -12dB +6dB ATT ALC ADC -6dB -6dB -0.5dB -6dB +5.5dB -6dB +6dB - 24 - [AK5365 ] 0dBFS -0.5dBFS -6dBFS -12dBFS 0dBFS -0.5dBFS -6dBFS -12dBFS 2002/08 ...

Page 25

... Note : After ALC operation is disabled, the IPGA changes to the last written data during or before ALC operation. MS0164-E-01 Manual Mode Set (SEL2-0 bits or SEL2-0 pins) WR (ZTM1-0, WTM1-0, LTM1-0) WR (LMAT, RATT, LMTH) WR (REF7-0) WR (IPGA7-0) (1) WR (ALC = “1”) (2) ALC Operation No Finish ALC mode? (1) Yes WR (ALC = “0”) (2) Finish ALC mode and return to manual mode Note : WR : Write - 25 - [AK5365 ] 2002/08 ...

Page 26

... Digital output delay from the analog input is called the group delay (GD). (3) If the soft mute is cancelled before the mute, the attenuation is discontinued and returned to IPGA value. MS0164-E-01 ( (2) Figure 13. Soft Mute Function within 1024 LRCK cycles (1024/fs [AK5365 ] within 1024 LRCK ( 2002/08 ...

Page 27

... Control Data MS0164-E-01 2 C-bus control mode. C1 bit C0 bit L 0 Fixed to “1” Fixed to “1” 2 Table 12. Chip address in I C-bus control Figure 14. Serial Control I/F Timing - 27 - [AK5365 ] 2002/08 ...

Page 28

... The second byte consists of the control register address of the AK5365. The format is MSB first, and those most significant 3-bits are fixed to zeros (Figure 17). The data after the second byte contains control data. The format is MSB first, 8bits (Figure 18) ...

Page 29

... ASAHI KASEI (2)-2. READ Operations Set the R/W bit = “1” for the READ operation of the AK5365. After transmission of data, the master can read the next address’s data by generating an acknowledge instead of terminating the write cycle after the receipt of the first data word. ...

Page 30

... MASTER S START CONDITION SDA SCL MS0164-E-01 Figure 21. START and STOP Conditions Figure 22. Acknowledge on the I C-Bus data line change stable; of data data valid allowed 2 Figure 23. Bit Transfer on the I C-Bus - 30 - [AK5365 ] P stop condition not acknowledge acknowledge 8 9 clock pulse for acknowledgement 2002/08 ...

Page 31

... MSB justified “H” : 24bit I Note : The SEL2-0 pins should be fixed to “LLL” if the AK5365 is controlled by the SEL2-0 bits, because the setting of the SEL2-0 pins are prior to the SEL2-0 bits setting. Other Functions are ORed between pin and register. ...

Page 32

... IPGA and ADC do not operate. The contents of all register are not initialized and enabled to write to the registers. When MCLK and LRCK are changed not necessary to reset by the PDN pin or PWN bit because the AK5365 builds in reset-free circuit. However, it can be reduced the noise by reset. Addr Register Name ...

Page 33

... Table 14. ALC recovery waiting time Zero crossing timeout period 288/fs 1152/fs 2304/fs 4608/fs Table 15. Zero crossing timeout ALC limiter operation period 3/fs 6/fs 12/fs 24/fs Table 16. ALC limiter period - 33 - [AK5365 ZTM1 ZTM0 WTM1 WTM0 @fs=48kHz 6ms 24ms 48ms ...

Page 34

... IPGA changes to the last written data by zero-crossing or time-out. In case of writing to the DATT area under 7FH (Table 17) of IPGL/R registers, the DATT changes even if ALC is enabled. MS0164-E- IPGL6 IPGL5 IPGL4 IPGR6 IPGR5 IPGR4 [AK5365 IPGL3 IPGL2 IPGL1 IPGL0 IPGR3 IPGR2 IPGR1 IPGR0 2002/08 ...

Page 35

... External 128 levels are converted to internal 0.43 24.64 8032 linear levels of DATT. Internal DATT 0.30 24.94 soft-changes between data 30.82 0.58 DATT =2 33) – 33 0.46 31.29 0.32 31. 0.67 38.18 38.73 0.54 39.11 0. 0.99 47.73 0.83 48.55 0.60 49. 58.10 1.58 60.03 1.94 2.50 62.53 3.52 66.05 6.02 72.07 MUTE Table 17. IPGA Code Table - 35 - [AK5365 IPGA Analog volume with 0.5dB step DATT m: MSB 3-bits of data l: LSB 4-bits of data 2002/08 ] ...

Page 36

... Table 18. ALC limiter ATT step RATT Gain Step 0 1 Default 1 2 Table 19. ALC recovery gain step ALC Recovery Waiting Counter Reset Level 0.5dBFS 0.5dBFS ALC Output 2.0dBFS 2.0dBFS ALC Output - 36 - [AK5365 LMTH RATT LMAT Default 2.5dBFS 4.0dBFS 2002/08 ...

Page 37

... The REF7-0 bits should not be set up except for Table 21. Table 21. Reference value at ALC recovery operation MS0164-E- REF7 REF6 REF5 REF4 DATA (hex) Gain (dB) 98H +12.0 97H +11.5 96H +11.0 95H +10 89H +4.5 Default : : 81H +0.5 80H [AK5365 REF3 REF2 REF1 REF0 2002/08 ] ...

Page 38

... Note: - AVSS and DVSS of the AK5365 should be distributed separately from the ground of external digital devices (MPU, DSP etc.). - When LOUT/ROUT drives a capacitive load, resistors should be added in series between LOUT/ROUT and capacitive load. - All input pins except pull-down pin (ALC, SMUTE pins) should not be left floating. ...

Page 39

... The ADC output data format 2’s compliment. The internal HPF removes the DC offset. The AK5365 samples the analog inputs at 64fs. The digital filter rejects noise above the stop band except for multiples of 64fs. The AK5365 includes an anti-aliasing filter (RC filter) to attenuate a noise around 64fs. ...

Page 40

... ASAHI KASEI 44pin LQFP (Unit: mm) 12.80 ± 0.30 10. 0.37 ± 0.10 0.15 Material & Lead finish Package molding compound: Lead frame material: Lead frame surface treatment: MS0164-E-01 PACKAGE 1.70max 0° 10° ~ 0.60 ± 0.20 Epoxy Cu Solder (Pb free) plate - 40 - [AK5365 ] 0 ~ 0.2 0.17 ± 0.05 2002/08 ...

Page 41

... AKM harmless from any and all claims arising from the use of said product in the absence of such notification. MS0164-E-01 MARKING AKM AK5365VQ XXXXXXX Date Code Identifier (7 digits) IMPORTANT NOTICE - 41 - [AK5365 ] 2002/08 ...

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