ak5365 AKM Semiconductor, Inc., ak5365 Datasheet - Page 28

• Manufacturer Part Number: ak5365
• Description: 24-bit 96khz ?? Adc With Selector/pga/alc
• Manufacturer: AKM Semiconductor, Inc.

ASAHI KASEI
(2) I
The AK5365 supports the standard-mode I
system (max: 400kHz).
(2)-1. WRITE Operations
Figure 15 shows the data transfer sequence for the I
HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition (Figure 21). After the START
condition, a slave address is sent. This address is 7 bits long followed by an eighth bit that is a data direction bit (R/W). The
most significant five bits of the slave address are fixed as “00100”. The next one bit are CAD1 (device address bits). This
one bit identify the specific device on the bus. The hard-wired input pin (CAD1 pin) set these device address bits (Figure
16). If the slave address matches that of the AK5365, the AK5365 generates an acknowledge and the operation is executed.
The master must generate the acknowledge-related clock pulse and release the SDA line (HIGH) during the acknowledge
clock pulse (Figure 22). A R/W bit value of “1” indicates that the read operation is to be executed. A “0” indicates that the
write operation is to be executed.
The second byte consists of the control register address of the AK5365. The format is MSB first, and those most significant
3-bits are fixed to zeros (Figure 17). The data after the second byte contains control data. The format is MSB first, 8bits
(Figure 18). The AK5365 generates an acknowledge after each byte has been received. A data transfer is always terminated
by a STOP condition generated by the master. A LOW to HIGH transition on the SDA line while SCL is HIGH defines a
STOP condition (Figure 21).
The AK5365 can perform more than one byte write operation per sequence. After receipt of the third byte the AK5365
generates an acknowledge and awaits the next data. The master can transmit more than one byte instead of terminating the
write cycle after the first data byte is transferred. After receiving each data packet the internal 5-bit address counter is
incremented by one, and the next data is automatically taken into the next address. If the address exceeds 07H prior to
generating the stop condition, the address counter will “roll over” to 00H and the previous data will be overwritten.
The data on the SDA line must remain stable during the HIGH period of the clock. The HIGH or LOW state of the data line
can only change when the clock signal on the SCL line is LOW (Figure 23) except for the START and STOP conditions.
MS0164-E-01
2
C-bus Control Mode (CTRL pin = “H”)
SDA
S
T
A
R
T
S
Slave
Address
D7
0
0
R/W="0"
Figure 15. Data Transfer Sequence at the I
A
C
K
D6
0
0
Sub
Address(n)
Figure 18. Byte Structure after the second byte
(CAD1 should match with CAD1 pin.)
2
C-bus (max: 100kHz). The AK5365 does not support a fast-mode I
D5
1
0
Figure 17. The Second Byte
Figure 16. The First Byte
C
A
K
2
C-bus mode. All commands are preceded by a START condition. A
Data(n)
A4
D4
0
- 28 -
A
C
K
A3
D3
0
Data(n+1)
CAD1
2
A2
D2
C-Bus Mode
C
A
K
D1
A1
1
C
A
K
Data(n+x)
R/W
A0
D0
A
C
K
S
T
O
P
P
[AK5365
2
C-bus
2002/08
]