ak5365 AKM Semiconductor, Inc., ak5365 Datasheet - Page 14

• Manufacturer Part Number: ak5365
• Description: 24-bit 96khz ?? Adc With Selector/pga/alc
• Manufacturer: AKM Semiconductor, Inc.

ASAHI KASEI
MCLK (256fs/384fs/512fs), BICK (48fs ) and LRCK (fs) clocks are required in slave mode. The LRCK clock input must
be synchronized with MCLK, however the phase is not critical. MCLK frequency is automatically detected in slave mode.
Table 1 shows the relationship of typical sampling frequency and the system clock frequency.
MCLK (256fs/384fs/512fs) is required in master mode. MCLK frequency is selected by CKS1-0 bits as shown in Table 2.
In master mode, after setting CKS1-0 bits, there is a possibility the frequency and duty of LRCK and BICK outputs become
an abnormal state.
All external clocks (MCLK, BICK and LRCK) must be present unless PDN pin = “L” and PWN bit = “1”. If these clocks
are not provided, the AK5365 may draw excess current due to its use of internal dynamically refreshed logic. If the external
clocks are not present, place the AK5365 in power-down mode (PDN pin = “L” or PWN bit = “0”). In master mode, the
master clock (MCLK) must be provided unless PDN pin = “L”.
Two kinds of data formats can be chosen with the DIF bit (Table 3) and the CTRL pin (Table 4). The DIF bit and CTRL pin
are ORed between pin and register. In both modes, the serial data is in MSB first, 2’s compliment format. The SDTO is
clocked out on the falling edge of BICK. The audio interface supports both master and slave modes. In master mode, BICK
and LRCK are output with the BICK frequency fixed to 64fs and the LRCK frequency fixed to 1fs.
MS0164-E-01
System Clock
Audio Interface Format
Mode
Mode
0
1
0
1
CKS1
0
0
1
1
44.1kHz
CTRL pin
32kHz
48kHz
96kHz
DIF bit
fs
H
L
0
1
Table 2. Master clock frequency select (Master mode)
CKS0
Table 3. Audio Interface Format (CTRL pin = “L”)
Table 4. Audio Interface Format (DIF bit = “0”)
0
1
0
1
24bit, I
Table 1. System clock example (Slave mode)
24bit, MSB justified
24bit, I
24bit, MSB justified
11.2896MHz
12.288MHz
24.576MHz
8.192MHz
256fs
2
SDTO
S Compatible
OPERATION OVERVIEW
2
SDTO
S Compatible
32kHz
256fs
512fs
384fs
N/A
fs
- 14 -
16.9344MHz
12.288MHz
18.432MHz
48kHz
LRCK
MCLK
LRCK
H/L
L/H
384fs
N/A
H/L
L/H
MCLK
48kHz
BICK
BICK
48fs
48fs
48fs
48fs
256fs
N/A
N/A
N/A
22.5792MHz
16.384MHz
24.576MHz
fs
Figure 1
Figure 2
512fs
N/A
Figure
Figure 1
Figure 2
96kHz
Figure
Default
Default
[AK5365
2002/08
]