ak5365 AKM Semiconductor, Inc., ak5365 Datasheet - Page 36

• Manufacturer Part Number: ak5365
• Description: 24-bit 96khz ?? Adc With Selector/pga/alc
• Manufacturer: AKM Semiconductor, Inc.

ASAHI KASEI
LMAT: ALC Limiter ATT step (see Table 18)
RATT: ALC Recovery gain step (see Table 19)
LMTH: ALC Limiter detection level / Recovery waiting counter reset level (see Table 20)
FR: ALC fast recovery
ALC:
ZELMN: Zero crossing enable flag at ALC limiter operation
MS0164-E-01
Addr
06H
Register Name
ALC Mode Control 1
During the ALC limiter operation, when either Lch or Rch exceeds the ALC limiter detection level set by LMTH
bit, the number of steps attenuated from the current IPGA value is set. For example, when the current IPGA value
is 94H and the LMAT bit = “1”, the IPGA transition to 92H when the ALC limiter operation starts, resulting in the
input signal level being attenuated by 1dB (=0.5dB x 2).
During the ALC recovery operation, the number of steps changed from the current IPGA value is set. For example,
when the current IPGA value is 82H and RATT bit = “1” is set, the IPGA changes to 84H by the ALC recovery
operation and the output signal level is gained up by 1dB (=0.5dB x 2). When the IPGA value exceeds the
reference level (REF7-0 bits), the IPGA value does not increase.
The ALC limiter detection level and the ALC recovery counter reset level may be offset by about 2dB.
When the impulse noise is input, the ALC recovery operation becomes faster than a normal recovery operation.
ALC enable flag
When the ZELMN bit = “0”, the IPGA of each L/R channel perform a zero crossing or timeout independently. The
zero crossing timeout is the same as the ALC recovery operation. When the ZELMN bit = “1”, the IPGA value is
changed immediately. The ALC Limiter period can be set up by a ZTM 1-0 bits when ZELMN bit = “0”, it can be
set up by a LTM1-0 bits when ZELMN bit = “1”
LMTH
Default
0 : Disable
1 : Enable (Default)
0 : ALC Disable (Default)
1 : ALC Enable
0 : Enable
1 : Disable (Default)
0
1
ALC Limiter Detection Level
Table 20. ALC Limiter detection level / Recovery waiting counter reset level
ALC Output
ALC Output
D7
0
0
0.5dBFS
2.0dBFS
Table 19. ALC recovery gain step
LMAT
RATT
Table 18. ALC limiter ATT step
D6
0
1
0
1
0
0
ZELMN
Gain Step
ALC Recovery Waiting Counter Reset Level
ATT Step
D5
- 36 -
1
1
2
1
2
0.5dBFS
2.0dBFS
ALC
D4
0
Default
Default
ALC Output
ALC Output
D3
FR
1
2.5dBFS
4.0dBFS
LMTH
D2
0
RATT
D1
0
Default
[AK5365
2002/08
LMAT
D0
0
]