m24l48512d Elite Semiconductor Memory Technology Inc., m24l48512d Datasheet - Page 4

• Manufacturer Part Number: m24l48512d
• Description: 4-mbit 512k X 8 Pseudo Static Ram
• Manufacturer: Elite Semiconductor Memory Technology Inc.

ESMT
Thermal Resistance[6]
Parameter
θ
θ
AC Test Loads and Waveforms
Switching Characteristics (Over the Operating Range)[7]
Read Cycle
t
t
t
t
t
t
t
t
t
t
Write Cycle[10]
t
t
t
t
Notes:
7. Test conditions assume signal transition time of 1 V/ns or higher, timing reference levels of V
8. t
9. High-Z and Low-Z parameters are characterized and are not 100% tested.
10.The internal write time of the memory is defined by the overlap of WE ,
11.To achieve 55-ns performance, the read access should be CE controlled. In this case t
Elite Semiconductor Memory Technology Inc.
Parameter
RC
AA
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
SK
WC
SCE
AW
HA
JA
JC
V
to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing
should be referenced to the edge of the signal that terminates write.
satisfied when the addresses are stable prior to chip enable going active. For the 70-ns cycle, the addresses must be stable
within 10 ns after the start of the read cycle.
HZOE
[11]
CC(typ)
, t
, and output loading of the specified I
HZCE
, and t
Parameters
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
9]
9]
Address Skew
Write Cycle Time
Address Set-up to Write End
Address Hold from Write End
CE
CE
CE
CE
OE LOW to Data Valid
OE LOW to Low Z[8, 9]
OE HIGH to High Z[8, 9]
Thermal Resistance (Junction to Ambient)
Thermal Resistance (Junction to Case)
1
1
1
1
R
V
R1
R2
HZWE
TH
TH
LOW and CE2 HIGH to Data Valid
LOW and CE2 HIGH to Low Z[8,
HIGH and CE2 LOW to High Z[8,
LOW and CE2 HIGH to Write End
transitions are measured when the outputs enter a high-impedance state.
Description
Description
OL
/I
OH
and 30-pF load capacitance.
55
Min.
3.0V V
55
45
45
5
5
2
0
22000
22000
11000
[11]
1.50
Test
methods and procedures for measuring
thermal impedance, per EIA/JESD51.
–55
CC
Max.
conditions
55
55
25
25
25
0
CE
Test Conditions
1
Min.
= V
60
60
45
45
8
5
2
0
follow
IL
, and CE2 = V
–60
standard
Publication Date: Jul. 2008
Max.
ACE
Revision: 1.1
60
60
25
25
25
5
CC(typ)
M24L48512DA
is the critical parameter and t
IH
/2, input pulse levels of 0V to
. All signals must be ACTIVE
test
Min.
70
10
70
60
55
5
5
0
Unit
Ω
Ω
Ω
V
VFBGA
–70
55
17
Max.
70
70
35
25
25
10
4/12
Unit
°C/W
°C/W
Unit
SK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
is