m52d32321a Elite Semiconductor Memory Technology Inc., m52d32321a Datasheet - Page 2
![no-image](/images/no-image-200.jpg)
m52d32321a
Manufacturer Part Number
m52d32321a
Description
512k X 32bit X 2banks Mobile Synchronous Dram
Manufacturer
Elite Semiconductor Memory Technology Inc.
Datasheet
1.M52D32321A.pdf
(30 pages)
ESMT
FUNCTIONAL BLOCK DIAGRAM
PIN FUNCTION DESCRIPTION
Elite Semiconductor Memory Technology Inc.
CLK
CKE
A0 ~ A10
BA
DQM0~3
DQ0 ~ 31
VDD/VSS
VDDQ/VSSQ
N.C/RFU
CS
RAS
CAS
WE
Pin
System Clock
Chip Select
Clock Enable
Address
Bank Select Address
Row Address Strobe
Column Address Strobe
Write Enable
Data Input / Output Mask
Data Input / Output
Power Supply/Ground
Data Output
Power/Ground
No Connection/
Reserved for Future Use
ADD
CLK
LCKE
Name
CLK
LRAS
CKE
Bank Select
LCBR
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM.
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
Row / column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA10, column address : CA0 ~ CA7
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS , WE active.
Makes data output Hi-Z, t
Blocks data input when DQM active.
Data inputs/outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide improved
noise immunity.
This pin is recommended to be left No Connection on the device.
CS
LWE
Timing Register
RAS
LCAS
CAS
Programming Register
Data Input Register
Latency & Burst Length
Column Decoder
512K x 32
512K x 32
WE
SHZ
after the clock and masks the output.
L(U)DQM
LWCBR
Input Function
LDQM
Revision : 1.6
Publication Date : May 2009
M52D32321A
LWE
LDQM
DQi
2/30