f25l32pa Elite Semiconductor Memory Technology Inc., f25l32pa Datasheet - Page 12

• Manufacturer Part Number: f25l32pa
• Description: 3v Only 32 Mbit Serial Flash Memory With Dual
• Manufacturer: Elite Semiconductor Memory Technology Inc.

ESMT
INSTRUCTIONS
Instructions are used to Read, Write (Erase and Program), and
configure the device. The instruction bus cycles are 8 bits each
for commands (Op Code), data, and addresses. Prior to
executing any Page Program, Write Status Register, Sector
Erase, Block Erase, or Chip Erase instructions, the Write Enable
(WREN) instruction must be executed first. The complete list of
the instructions is provided in Table 5. All instructions are
synchronized off a high to low transition of CE . Inputs will be
accepted on the rising edge of SCK starting with the most
significant bit. CE must be driven low before an instruction is
Operation
Read
Fast Read
Fast Read Dual Output
Fast Read Dual I/O
Sector Erase
Block Erase
Chip Erase
Page Program (PP)
Mode Bit Reset
Deep Power Down (DP)
Read Status Register
(RDSR)
Enable Write Status
Register (EWSR)
Write Status Register
(WRSR)
Write Enable (WREN)
Write Disable (WRDI)/ Exit
secured OTP mode
Enter secured OTP mode
(ENSO)
Release from Deep Power
Down (RDP)
Read Electronic Signature
(RES)
RES in secured OTP mode
& not lock down
RES in secured OTP mode
& lock down
Elite Semiconductor Memory Technology Inc.
8
6
7
4,
4
(64K Byte)
(4K Byte)
15
7
12, 14
10
12,13
100
33
50
Max.
Freq
～
MHz
MHz
MHz
60H /
C7H
FFH
05H
50H
01H
06H
04H
B9h
0BH
B1H
03H
ABH Hi-Z
ABH Hi-Z
ABH Hi-Z
ABH Hi-Z
D8H
20H
02H
S
IN
BBH
3BH
1
S
Hi-Z A
Hi-Z A
Hi-Z A
Hi-Z A
Hi-Z
Hi-Z A
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Table 5: Device Operation Instruction
OUT
(S
FFH
23
23
23
23
23
D
S
7
X
X
X
X
-
-
-
-
-A
-A
-A
-A
-
-A
-
-
-S
IN
IN
A
A
16
16
16
16
16
0
23
)
23
2
-A
-A
(S
16
S
D
Hi-Z
Hi-Z
8
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
7
OUT
OUT
X
X
X
-
-
-S
-
-
-
-
-
0
)
(S
A
A
A
A
A
A
entered and must be driven high after the last bit of the instruction
has been shifted in (except for Read, Read ID, Read Status
Register, Read Electronic Signature instructions). Any low to high
transition on CE , before receiving the last bit of an instruction
bus cycle, will terminate the instruction in progress and return the
device to the standby mode.
Instruction commands (Op Code), addresses, and data are all
input from the most significant bit (MSB) first.
15
15
15
15
15
D
15
S
7
X
X
X
-A
-
-
-
-
-
-
-
-
-
IN
-A
-A
-A
-A
-A
IN
-S
A
15
0,
8
8
8
8
8
8
3
)
-A
M
7
S
8
Hi-Z A
Hi-Z A
Hi-Z A
Hi-Z A
Hi-Z A
Hi-Z
-M
OUT
X
X
X
-
-
-
-
-
-
-
-
-
Bus Cycle
0
S
7
7
7
7
7
-.
-.
X
X
X
-A
-A
-A
-A
-
-A
-
-
-
-
-
-
-
D
IN
A
OUT0~1
0
0
0
0
0
7
4
-A
1~3
S
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
0
OUT
X
X
X
-
-
-
-
-
-
-
-
-
-
D
S
Publication Date: Mar. 2009
Revision: 1.0
X
X
X
X
X
-
-
-
IN0
-
-
-
-
-
-
-
-
-
IN
cont.
X
5
D
S
Hi-Z
15H
35H
75H
OUT0
OUT
X
-
-
-
-
-
-
-
-
-
-
-
-
F25L32PA
D
S
X
X
D
-
-
-
IN1
-
-
-
-
-
-
-
-
-
-
-
-
IN
OUT0~1
6
-
D
D
S
Hi-Z
OUT1
OUT0
OUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Up to
bytes
256
S
X
X
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
IN
12/36
cont.
N
-
cont.
cont.
S
Hi-Z
OUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-