mt90503 Zarlink Semiconductor, mt90503 Datasheet - Page 35

• Manufacturer Part Number: mt90503
• Description: 2048vc Aal1 Sar
• Manufacturer: Zarlink Semiconductor

4.1.1
The CPU interface provides a programmable global interrupt capability. The interrupt signal names are ‘interrupt1’
and ‘interrupt2’, pins AH11 and AG11 respectively. Both interrupts have programmability to select their polarity
(open collector drive) via registers ‘interrupt1_conf’ and ‘interrupt2_conf’ addresses 0224h and 0226h respectively.
Interrupt1 accommodates a capability to program a minimum acceptable period between interrupts. The period is
programmed in s units via ‘interrupt1_conf’ register. This provides a ‘frequency interrupt controller’ facility and
masks the assertion of further interrupts until the specified period has elapsed. The mask period will commence
when the interrupt1_treated[15], register interrupt_flags address 0220h is set. When Interrupt2 is enabled it is
always activated when an interrupt condition occurs. Interrupt pins are always tri-stated when inactive.
The operation of the CPU interrupt network is common for all modules. When an interrupt is asserted an
interrupt flag is set to identify the module where the interrupt was generated. Each module has one or more
Interrupt Enable Status Registers where a set interrupt enable bit identifies the source of the interrupt. On
completion of the ISR the interrupt must be cleared as the interrupt will remain asserted until it is de-asserted by
the user. All Interrupt Enable Status Registers have a symmetrical Status Register. Hence, the bit positioning of
the interrupt enables and the associated status bits are identical.
4.1.1.1
Upon the initialization of the Global Interrupt pins the following methodology is adopted to identify the source of the
interrupt. For this example Interrupt2 is employed and the CPU module will be the source of the interrupt.
4.1.1.2
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4.1.1.3
When interrupt2 is asserted (‘interrupt2’ pin):
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Set interrupt polarity, register interrupt2_conf[15:14].
Enable Interrupt2 for the CPU module, register interrupt2_enable[0] 022Ch. The MT90503 will generate an
interrupt on interrupt2 according to the modules enabled in interrupt2_enable.
Set the individual CPU interrupt sources by enabling the respective bits in the `status0_ie' 0104h register.
Within the `status0_ie' register there are two possible interrupt sources: internal_read_timeout_ie and
inmo_read_done_ie. In the MT90503 Register Description the interrupt bits are labelled IE (Interrupt Enable)
in the ‘Type’ column. This register offers the facility to mask/disable unwanted interrupts.
Read the interrupt flags to ascertain the module raising the interrupt. The CPU module interrupt flag is
located in register interrupt_flags[0] 0220h, this bit is named cpureg_interrupt_active.
If the cpureg_interrupt_active bit is set, locate the source of the CPU interrupt by reading the ‘status0’
register 0102h, either internal_read_timeout and/or inmo_read_done.
The associated status register ‘status0’ 0102h contains internal_read_timeout and inmo_read_done bits.
Therefore, to de-assert the interrupt the user must write a 1 to register 0102h bits 3 or 4,
internal_read_timeout and inmo_read_done respectively. Only then will the interrupt be de-asserted.
CPU Interrupts
Example Interrupt Flow
Interrupt Initialization
Interrupt Servicing
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MT90503
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Data Sheet