mt90503 Zarlink Semiconductor, mt90503 Datasheet - Page 45

• Manufacturer Part Number: mt90503
• Description: 2048vc Aal1 Sar
• Manufacturer: Zarlink Semiconductor

4.2.4.2
The RX Byte Write bits remain the same to allow the insertion of null patterns as for regular channels. The Mode
bits, indicate the possible configurations and combinations of multiframing and CAS insertion: “0100” is E1, “0110”
is T1, and toggling the lowest bit of either of the numbers indicates that the FASTCAS method of transmitting the
data and CAS bytes is being used. FASTCAS is used to lower the latency of Circuit Emulation cells. When using
the FASTCAS mode, the multiframe pointer is not used and multiframe integrity is therefore not maintained.
In addition, special fields for CAS are added in the two additional words of the structure. The CAS WE (CAS Write
Enable) bits are used to determine if the CAS is written back.
The TX_CAS field is used so the CPU can insert values of CAS, in place of values from the TDM bus; the RX CAS
value is used to compensate for underruns.
The Last TX CAS field is used to detect when the CAS value received on the TDM bus has changed. When a CAS
value is received, it is written back to the Last TX CAS field in the structure. Whenever a new value arrives, it is
compared to the last value. If there is a difference, a CAS change signal is sent to the registers, and the new CAS
value is written to the CAS change buffer in the external memory.
The Frame Offset field is used to store the offset between the internal and external multiframes in the TX direction.
When the TDM bus first obtains an external multiframe, it writes the offset field to the correct value between 0 and
CAS Operation
TX/RX Circular Buffer Address and Size: Address and size of the circular buffer in the data memory
to which data bytes will be written.
I: Initialized Bit. Written by ‘0’ by software, set by hardware when the channel starts being treated.
Mode: Channel Mode of operation.
RBW: RX Byte Write. Selects byte that will be written in the low bytes of the data memory word where
the TX TDM bytes are written.
CASWE : CAS write enable.
TX CAS Force : TX CAS value that must be written to bypass the CAS bits from the associated odd
stream.
EI: CAS Enable Ignore. If set, the CAS Enable bit (SFS Bit) will be ignored. Instead, the CAS will be
latched at one point for each 16/24 consecutive bytes (for E1 and T1 respectively).
RX CAS UR : RX CAS value that will be sent in case of an underrun situation on the RX_SAR side.
CM: Cas Monitor. When ‘1’, any change in the TX CAS value will be reported to the CPU.
Last TX CAS : Last Value of the TX CAS received from the TDM bus.
FS Offset : Frame Offset that must be added in order for internal and external multiframes to coincide.
Initialize to “00000” by software.
“0100”=E1 Strict Multiframing;
“0101”=E1 FASTCAS;
“0110”=T1 Strict Multiframing;
“0111”=T1 FASTCAS;
others=Reserved.
“00”=Do not write over the low byte;
“01”=Write a null byte (usually FFh);
“10”=Write silence pattern A;
“11”=Write silence pattern B.
“x0”=Leave CAS bits in RX Circular Buffer untouched;
“x1”=WriteRX CAS UR in RX Circular Buffer in case of underrun;
“0x”=Write CAS bits present on the associated odd stream to the TX Circular Buffer;
“1x”=WriteTX CAS Force field in order to bypass the CAS bits from the associated odd stream.
Reserved
Figure 11 - TDM Channel Association: TX Channels (CAS mode)
+0
+2
+4
+6
b15
RX CAS UR
b14
Mode
b13
TX/RX Circular Buffer Address and Size
b12
b11
RBW
b10
Zarlink Semiconductor Inc.
b9
1
0
MT90503
b8
0
0
b7
45
TX CAS Force
FS Offset
b6
b5
b4
b3
EI
Last TX CAS
CM
b2
CASWE
b1
b0
I
Data Sheet