mt90503 Zarlink Semiconductor, mt90503 Datasheet - Page 87

• Manufacturer Part Number: mt90503
• Description: 2048vc Aal1 Sar
• Manufacturer: Zarlink Semiconductor

4.6
4.6.1
The purpose of the clock recovery module is to synchronise the TDM clock domain of the MT90503 with other
devices on the network through information transmitted across the ATM link. Clock recovery is necessary only
when the MT90503 is operating as the TDM clock master.
The clock recovery system is composed of several sub-components:
4.6.1.1
The point generation modules permit SRTS and/or adaptive clock recovery to be performed by the MT90503. The
two modules provide the flexibility to have a back up clock recovery process operating from another VC and/or of
the complementary type. These modules generate points which are written to control memory and subsequently
used by the clock recovery algorithm.
4.6.1.2
The SRTS generating module, is employed to generate the 4-bit outgoing RTS value.
4.6.1.3
The integer divisor clock (idclk) modules are designed to manipulate any incoming or internal clocks and produce
an 8kHz idclk. They provide the flexibility of inverting the clock before or after division, option of setting the duty
Clock Recovery Module
Overview
PHY Device
rxclav
rxdata
rxenb
Two Point Generation Modules
One SRTS (synchronous residual time stamp) Generating Module
Three Integer Divisor Clock Modules
rxsoc
rxpar
rxclk
txdata
txclav
txenb
txsoc
txpar
txclk
Port A, ATM Mode
MT90503 - ATM Mode
txa_clk (H3)
txa_enb (H2)
txa_clav (J5)
txa_soc (N2)
txa_d (N4 . . .)
txa_par (N3)
rxa_clk (C6)
rxa_enb (B6)
rxa_clav (A6)
rxa_soc (H4)
rxa_d (G3 . . .)
rxa_par (G2)
Figure 42 - External UTOPIA Interface
Zarlink Semiconductor Inc.
MT90503
87
ATM Device
txdata
txclav
txenb
txsoc
txpar
txclk
rxdata
rxclav
rxenb
rxsoc
rxpar
rxclk
Port A, PHY mode
MT90503 - PHY Mode
txa_clk (H3)
txa_enb ( J5 )
txa_clav ( H2 )
txa_soc (N2)
txa_d (N4 . . .)
txa_par (N3)
rxa_clk (C6)
rxa_enb ( A6 )
rxa_clav ( B6 )
rxa_soc (H4)
rxa_d (G3 . . .)
rxa_par (G2)
Data Sheet