mt90503 Zarlink Semiconductor, mt90503 Datasheet - Page 88

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mt90503

Manufacturer Part Number
mt90503
Description
2048vc Aal1 Sar
Manufacturer
Zarlink Semiconductor
Datasheet

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cycle to 50%, 16-bit division and checking of the frequency (within a desired range). Along with the idclk_loss
signals, idclk’s are suited to being sent to an external PLL.
4.6.1.4
The precise clock (pclk) modules are used to divide mclk down to pclk_a and pclk_b. Each module has a pclk_loss
indicator which can be employed in tandem with the pclk signal to be routed to an external PLL. The division of mclk
is performed with a 16-bit integer and a 16-bit fraction, allowing for precise specification of the pclk frequency.
These modules are ideally suited to being programmed by the clock recovery algorithm to generate the recovered
clock.
4.6.1.5
The 11 multiplexers are: recov_a to recov_h, ct_netref1, ct_netref2 and local_netref_16m. recov_a through recov_h
and ct_netrefx are general I/O pins. Local_netref_16m is an internal node, used as the master clock for the TDM
section of the MT90503.
4.6.2
There are eleven multiplexers (see Table 28, “Source Selection,” on page 89) with 36 possible inputs each (see
Table 29, “idclk_a Register,” on page 91):
Multiplexers
Two Precise Clock Modules
Eleven Multiplexers
local_netref_16m
ct_netref1
ct_netref2
recov_a
recov_b
recov_c
recov_d
recov_e
recov_g
recov_h
recov_f
Signal
Table 27 - Multiplexer Registers
Zarlink Semiconductor Inc.
MT90503
88
Address
086Ah
0860h
0860h
0862h
0862h
0864h
0864h
0866h
0866h
0868h
0868h
Bits
13:8
13:8
13:8
13:8
13:8
5:0
5:0
5:0
5:0
5:0
5:0
Data Sheet

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