mt90503 Zarlink Semiconductor, mt90503 Datasheet - Page 64

• Manufacturer Part Number: mt90503
• Description: 2048vc Aal1 Sar
• Manufacturer: Zarlink Semiconductor

4.3.5
TX_SAR control structures are constructs in control memory which contain ATM cell information. When a frame
event is read from one of the 15 transmit event schedulers, an ATM cell is assembled. The scheduler event
contains the base address that points to the control structure that is used for assembling the ATM cell. The control
structure contains all of the fields that are required for assembling the ATM cell. The destination field in the control
structure is responsible for telling the UTOPIA Module the destination VC of the assembled ATM cell. For detailed
information regarding the destination field, refer to Table 22, 'Description of the Fields for the TX_SAR Control
Structure"‚ on page 65.
Figure 28 - TX_SAR Event Scheduler Pointer Flow and Control Structure shows a functional block diagram of an
example of transmit event scheduler interconnections and pointer flow to the TX_SAR control structure.
00000h
00008h
00070h
TDM Channel Association
TX_SAR Control Structures
Memory (Internal)
TX_SAR Control Structure
Scheduler 0’s Info
Scheduler List
TDM Channel 1 Pnt
TDM Channel 0 Pnt
TDM Channel 2 Pnt
Header of the
Structure
TSST 4093
TSST 4094
TSST 4095
TSST 0
TSST 1
TSST 2
Figure 28 - TX_SAR Event Scheduler Pointer Flow and Control Structure
Pointer to current
Frame in Scheduler
Note: All structures are in the Control memory unless otherwise specified
tx_sar_read_pnt
Byte read by
TX_SAR
tdm_write_pnt
Base address of control structure from Event 1
TDM Transmit
Byte written by
Zarlink Semiconductor Inc.
Scheduler 0, Frame 374
Scheduler 0, Frame 1
Scheduler 0, Frame 0
Scheduler 0
MT90503
64
(Same pointer in Channel Association
Memory and in TX_SAR Control Structure)
TX Side
TX/RX Circular Buffer Pointer
RX Side
Scheduler 0, Frame 1
TDM Channel 1’s Circular
Buffer (in the Data Memory)
Event 63
Event 0
Event 1
Data Sheet