mt90503 Zarlink Semiconductor, mt90503 Datasheet - Page 66

• Manufacturer Part Number: mt90503
• Description: 2048vc Aal1 Sar
• Manufacturer: Zarlink Semiconductor

SRTS
AAL
Field
Table 22 - Description of the Fields for the TX_SAR Control Structure (continued)
Synchronous
Residual
Time Stamp
Adaptation
Layer
Name of
Field
+0/b8:b7
+0/b6:b5
Offset /Bits
Address
Used
Byte
Zarlink Semiconductor Inc.
The SRTS bits indicate the generation of SRTS within the VC.
SRTS is either absent, enabled, or enabled and master. Many
VCs can be programmed to transmit SRTS, but only one can
request a new SRTS value. If many VCs transport SRTS, they
must all be of the same size, i.e., the same number of
channels, to ensure the validity of the values. If SRTS is
generated on the VC, it is packaged within the AAL1 byte of
cells 1, 3, 5 and 7 of an 8-cell cycle.
The SRTS field should never be enabled on CBR-AAL0 or
AAL5-VTOA VCs. If SRTS is enabled on multiple VCs, the
events must be mapped in such a way that an event that
generated cell # 0 for the master VC occurs before the event
that generates cell # 0 for all the other VCs.
The SRTS field bits are encoded as follows:
00 = No SRTS
01 = Reserved
10 = Send SRTS
11 = Send SRTS, and request a new SRTS value on Seq = 7
The AAL bits indicate the ATM format to be used to assemble
the cells in this structure.
The AAL field bits are decoded as follows:
00 = CBR AAL0. Consists of CBR data
01 = AAL5-VTOA. Includes a CRC and a payload size
indicator at the end of the cell
10 = AAL1 without pointer. Includes a Sequence number
packaged with the cell, as well as the possibility of transmitting
SRTS on the VC
11 = AAL1 with pointer. Includes a Sequence number
packaged with the cell, and the possibility of transmitting SRTS
on the VC
MT90503
66
Description of Field
Data Sheet