zl50058 Zarlink Semiconductor, zl50058 Datasheet - Page 19

• Manufacturer Part Number: zl50058
• Description: 12 K Channel Digital Switch With High Jitter Tolerance, Per Stream Rate Conversion 2, 4, 8, 16 Or 32 Mbps , 48 Input And 48 Output Streams
• Manufacturer: Zarlink Semiconductor

Pin Description (continued)
JTAG Control Signals
TCK
TMS
TDi
TDo
TRST
Power and Ground Pins
V
V
V
Pin Name
DD_IO
DD_CORE
DD_PLL
A14
D12
B13
C13
B14
D6, D11, D15,
F4, F17, K4,
L17, R4, R17,
U6, U10, U15
A7, B4, B12,
D14, K1, K20,
N3, P18, T17,
U16, V1, V5,
Y7, Y11, Y14
U12
Coordinates
Package
(272-ball
ZL50057
PBGA)
D10
B12
C11
C12
D11
E5, E6, E11,
E12, F5, F12,
G5, G12, H5,
H12, L5, L12,
M5, M12
E7, E8, E9,
E10, F6, F11,
J5, J12, K5,
K12, L6, L7,
L10, L11
M10
Coordinates
Package
(256-ball
ZL50058
PBGA)
Zarlink Semiconductor Inc.
ZL50057/8
Test Clock (5 V Tolerant Input).
Provides the clock to the JTAG test logic.
Test Mode Select (5 V Tolerant Input with Internal Pull-up).
JTAG signal that controls the state transitions of the TAP
controller.
Test Serial Data In (5 V Tolerant Input with Internal
Pull-up).
JTAG serial test instructions and data are shifted in on this pin.
Test Serial Data Out (5 V Tolerant Three-state Output).
JTAG serial data is output on this pin on the falling edge of
TCK. This pin is held in a high impedance state when JTAG is
not enabled.
Test Reset (5 V Tolerant Input with Internal Pull-up).
Asynchronously initializes the JTAG TAP controller to the
Test-Logic-Reset state. This pin must be pulsed LOW during
power-up for JTAG testing. This pin must be held LOW for
normal functional operation of the device.
Power Supply for Periphery Circuits: +3.3 V
Power Supply for Core Circuits: +1.8 V
Power Supply for Analog PLL: +1.8 V
19
Description
Data Sheet