zl50058 Zarlink Semiconductor, zl50058 Datasheet - Page 69

• Manufacturer Part Number: zl50058
• Description: 12 K Channel Digital Switch With High Jitter Tolerance, Per Stream Rate Conversion 2, 4, 8, 16 Or 32 Mbps , 48 Input And 48 Output Streams
• Manufacturer: Zarlink Semiconductor

14.3
Address 0002
The BER Test Control Register controls Backplane and Local port BER testing. It independently enables and
disables transmission and reception. It is configured as follows:
15:12
Bit
11
10
9
8
7
6
5
4
3
Bit Error Rate Test Control Register (BERCR)
SBERRXB
SBERTXB
Reserved
CBERB
LOCKB
PRSTB
PRBSB
CBERL
LOCKL
PRSTL
Name
H
.
Reset
Value
Table 23 - Bit Error Rate Test Control Register (BERCR) Bits
0
0
0
0
0
0
0
0
0
0
Reserved
Must be set to 0 for normal operation
Backplane Lock (READ ONLY)
This bit is automatically set HIGH when the receiver has locked to the incoming
data sequence. The bit is reset by a LOW to HIGH transition on SBERRXB.
PBER Reset for Backplane
A LOW to HIGH transition initializes the Backplane BER generator to the seed
value.
Clear Bit Error Rate Register for Backplane
A LOW to HIGH transition in this bit resets the Backplane internal bit error
counter and the Backplane Bit Error Register (BBERR) to zero.
Start Bit Error Rate Receiver for Backplane
A LOW to HIGH transition enables the Backplane BER receiver. The receiver
monitors incoming data for reception of the seed value. When detected, the
LOCK state is indicated (LOCKB), the receiver compares the incoming bits with
the reference generator for bit equality, and increments the Backplane Bit Error
Register (BBCR) on each failure.
When LOW, bit comparison is disabled and the error count is frozen.
Start Bit Error Rate Transmitter for Backplane
A LOW to HIGH transition starts the BER transmission on the Backplane.
When LOW, Backplane transmission is disabled.
BER Mode Select for Backplane
When HIGH, a PRBS sequence of length 2
port.
When LOW, a PRBS sequence of length 2
port.
Local Lock (READ ONLY)
This bit is automatically set HIGH when the receiver has locked to the incoming
data sequence. The bit is reset by a LOW to HIGH transition on SBERRXL
PBER Reset for Local
A LOW to HIGH transition initializes the Local BER generator to the seed value.
Clear Bit Error Rate Register for Local
A LOW to HIGH transition resets the Local internal bit error counter and the
Local Bit Error Register (LBERR) to zero.
Zarlink Semiconductor Inc.
ZL50057/8
69
Description
15
23
-1 is selected for the Backplane
-1 is selected for the Backplane
Data Sheet