zl50058 Zarlink Semiconductor, zl50058 Datasheet - Page 6

• Manufacturer Part Number: zl50058
• Description: 12 K Channel Digital Switch With High Jitter Tolerance, Per Stream Rate Conversion 2, 4, 8, 16 Or 32 Mbps , 48 Input And 48 Output Streams
• Manufacturer: Zarlink Semiconductor

Figure 1 - ZL50057/8 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2 - ZL50057 PBGA Connections (272 PBGA, 27mm x 27mm) Pin Diagram
Figure 3 - ZL50058 PBGA Connections (256 PBGA, 17mm x 17mm) Pin Diagram
Figure 4 - 12,288 x 12,288 Channels (16Mbps), Unidirectional Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 5 - 8,192 x 4,096 Channels (16Mbps), bi-directional Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 6 - 6,144 by 6,144 Channels Non-Blocking Bi-directional Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 7 - ST-BUS and GCI-Bus Input Timing Diagram for Different Data Rates . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 8 - Input and Output (Generated) Frame Pulse Alignment for Different Data Rates . . . . . . . . . . . . . . . . . 28
Figure 9 - Backplane and Local Input Channel Delay Timing Diagram (assuming 8Mbps operation) . . . . . . . . . . 30
Figure 10 - Backplane and Local Input Bit Delay Timing Diagram for Data Rate of 16Mbps. . . . . . . . . . . . . . . . . 31
Figure 11 - Backplane and Local Input Bit Delay or Sampling Point Selection Timing Diagram for Data Rate of
Figure 12 - Local and Backplane Output Advancement Timing Diagram for Data Rate of 16Mbps . . . . . . . . . . . 33
Figure 13 - Local Port External High Impedance Control Bit Timing (Non-32Mbps Mode) . . . . . . . . . . . . . . . . . . 37
Figure 14 - Local Port External High Impedance Control Timing (32Mbps Mode). . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 15 - Backplane Port External High Impedance Control Bit Timing (Non-32Mbps Mode) . . . . . . . . . . . . . . 45
Figure 16 - Backplane Port External High Impedance Control Timing (32Mbps Mode). . . . . . . . . . . . . . . . . . . . . 49
Figure 17 - Data Throughput Delay with Input Channel Delay Disabled, Input Ch0 Switched to Output Ch0 . . . . 51
Figure 18 - Data Throughput Delay with Input Channel Delay Disabled, Input Ch0 Switched to Output Ch13 . . . 51
Figure 19 - Data Throughput Delay with Input Channel Delay Disabled, Input Ch13 Switched to Output Ch0 . . . 51
Figure 20 - Data Throughput Delay with Input Channel Delay Enabled, Input Ch0 Switched to Output Ch0 . . . . 52
Figure 21 - Data Throughput Delay with Input Channel Delay Enabled, Input Ch0 Switched to Output Ch13 . . . 52
Figure 22 - Data Throughput Delay with Input Channel Delay Enabled, Input Ch13 Switched to Output Ch0 . . . 52
Figure 23 - Examples of BER Transmission Channels on a 16Mbps Output Stream . . . . . . . . . . . . . . . . . . . . . . 53
Figure 24 - Hardware RESET De-assertion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 25 - Frame Boundary Conditions, ST-BUS Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 26 - Frame Boundary Conditions, GCI-Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 27 - Input and Output Clock Timing Diagram for ST-BUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Figure 28 - Input and Output Clock Timing Diagram for GCI-Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Figure 29 - ST-BUS Local/Backplane Data Timing Diagram (8Mbps, 4Mbps, 2Mbps) . . . . . . . . . . . . . . . . . . . . . 97
Figure 30 - ST-BUS Local/Backplane Data Timing Diagram (32Mbps, 16Mbps). . . . . . . . . . . . . . . . . . . . . . . . . . 98
Figure 31 - GCI-Bus Local/Backplane Data Timing Diagram (8Mbps, 4Mbps, 2Mbps) . . . . . . . . . . . . . . . . . . . . . 99
Figure 32 - GCI-Bus Local/Backplane Data Timing Diagram (32Mbps, 16Mbps) . . . . . . . . . . . . . . . . . . . . . . . . 100
Figure 33 - Serial Output and External Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Figure 34 - Output Driver Enable (ODE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Figure 35 - Motorola Non-Multiplexed Bus Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure 36 - JTAG Test Port Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
(as viewed through top of package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
(as viewed through top of package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
8Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
List of Figures
Zarlink Semiconductor Inc.
ZL50057/8
6
Data Sheet