zl50058 Zarlink Semiconductor, zl50058 Datasheet - Page 57

• Manufacturer Part Number: zl50058
• Description: 12 K Channel Digital Switch With High Jitter Tolerance, Per Stream Rate Conversion 2, 4, 8, 16 Or 32 Mbps , 48 Input And 48 Output Streams
• Manufacturer: Zarlink Semiconductor

The Backplane Block Programming data bits, BBPD[2:0], of the Block Programming Register, will be loaded into
bits[15:13] respectively, of the Backplane Connection Memory. The remaining bit positions are loaded with zeros as
shown in Table 12.
The Block Programming Register bit, BPE will be automatically reset LOW within 125 µs, to indicate completion of
memory programming.
The Block Programming Mode can be terminated at any time prior to completion by clearing the BPE bit of the
Block Programming Register or the MBP bit of the Control Register.
Note that the default values (LOW) of LBPD[2:0] and BBPD[2:0] of the Block Programming Register, following a
device reset, can be used.
During reset, all output channels go HIGH or high impedance, depending on the value of the LORS and BORS
pins, irrespective of the values in bits[14:13] of the connection memory.
10.0
As operation of the memory BIST will corrupt existing data, this test must only be instigated when the device is
placed “out-of-service” or isolated from live traffic.
The memory BIST mode is enabled through the microprocessor port (Section 14.14, Memory BIST Register).
Internal BIST memory controllers generate the memory test pattern (S-march) and control the memory test. The
memory test result is monitored through the Memory BIST Register.
11.0
The ZL50057/8 JTAG interface conforms to the IEEE 1149.1 standard. The operation of the boundary-scan circuit
shall be controlled by an external Test Access Port (TAP) Controller.
11.1
The Test Access Port (TAP) consists of four input pins and one output pin described as follows:
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BBPD2
Test Clock Input (TCK)
TCK provides the clock for the TAP Controller and is independent of any on-chip clock. TCK permits the
shifting of test data into or out of the Boundary-Scan register cells under the control of the TAP Controller in
Boundary-Scan Mode.
Test Mode Select Input (TMS)
The TAP controller uses the logic signals applied to the TMS input to control test operations. The TMS
signals are sampled at the rising edge of the TCK pulse. This pin in internally pulled to V
driven from an external source.
Test Data Input (TDi)
Depending on the previously applied data to the TMS input, the serial input data applied to the TDi port is
connected either to the Instruction Register or to a Test Data Register. Both registers are described in
Section 11.2, TAP Registers. The applied input data is sampled at the rising edge of TCK pulses. This pin is
internally pulled to V
Test Data Output (TDo)
Depending on the previously applied sequence to the TMS input, the contents of either the instruction
register or data register are serially shifted out towards the TDo. The data out of the TDo is clocked on the
15
Test Access Port (TAP)
JTAG Port
Memory Built-In-Self-Test (BIST) Mode
BBPD1
14
Table 12 - Backplane Connection Memory in Block Programming Mode
DD_IO
BBPD0
13
when not driven from an external source.
12
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11
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Zarlink Semiconductor Inc.
ZL50057/8
10
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9
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8
0
7
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6
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5
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4
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3
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DD_IO
2
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Data Sheet
when not
1
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0
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