zl50058 Zarlink Semiconductor, zl50058 Datasheet - Page 76

• Manufacturer Part Number: zl50058
• Description: 12 K Channel Digital Switch With High Jitter Tolerance, Per Stream Rate Conversion 2, 4, 8, 16 Or 32 Mbps , 48 Input And 48 Output Streams
• Manufacturer: Zarlink Semiconductor

14.7.1
When SMPL_MODE = LOW, these five bits define the delay from the bit boundary that the receiver uses to sample
each input. Input bit delay adjustment can range up to 7
default sampling point is at the
This can be described as: no. of bits delay = BID[4:0] / 4
For example, if BID[4:0] is set to 10011 (19), the input bit delay = 19 *
When SMPL_MODE = HIGH, the binary value of BID[1:0] refers to the input bit sampling point (
refers to the integer bit delay value (0 to 7 bits). This means that bits can be delayed by an integer value of up to 7
and that the sampling point can vary from
Table 31 illustrates the bit delay and sampling point selection.
Backplane Input Delay Bits 4-0 (BID[4:0])
BID4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Table 31 - Backplane Input Bit Delay and Sampling Point Programming Table
BID3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
BIDn
BID2
3
/
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
4
bit location.
BID1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
/
4
to
Zarlink Semiconductor Inc.
4
ZL50057/8
/
BID0
4
in
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
/
4
76
3
/
bit increments.
4
SMPL_MODE
bit periods forward, with resolution of
Input Data
0 (Default)
Bit Delay
= LOW
1 1/4
1 1/2
1 3/4
2 1/4
2 1/2
2 3/4
3 1/4
3 1/2
3 3/4
4 1/4
4 1/2
4 3/4
5 1/4
5 1/2
5 3/4
1/4
1/2
3/4
1
2
3
4
5
1
/
4
= 4
Input Data
3
0 (Default)
Bit Delay
/
4.
0
0
0
1
1
1
1
2
2
2
2
3
3
3
3
4
4
4
4
5
5
5
5
SMPL_MODE
= HIGH
Input Data
Sampling
Point
1
3/4
4/4
1/4
2/4
3/4
4/4
1/4
2/4
3/4
4/4
1/4
2/4
3/4
4/4
1/4
2/4
3/4
4/4
1/4
2/4
3/4
4/4
1/4
2/4
1
/
4
/
4
to
bit period. The
Data Sheet
4
/
4
). BID[4:2]