zl50058 Zarlink Semiconductor, zl50058 Datasheet - Page 72

• Manufacturer Part Number: zl50058
• Description: 12 K Channel Digital Switch With High Jitter Tolerance, Per Stream Rate Conversion 2, 4, 8, 16 Or 32 Mbps , 48 Input And 48 Output Streams
• Manufacturer: Zarlink Semiconductor

14.5
Addresses 0023
There are sixteen Local Input Delay Registers (LIDR0 to LIDR15).
When the SMPL_MODE bit in the Control Register is LOW, the input data sampling point defaults to the 3/4 bit
location and LIDR0 to LIDR15 define the input bit fractional delay of each Local stream. The possible bit delay
adjustment is up to 7
When the SMPL_MODE bit is HIGH, LIDR0 to LIDR15 define the input bit sampling point as well as the integer bit
delay of each Local stream. The input bit sampling point can be adjusted in 1/4 bit increments. The bit delay can be
adjusted in 1 bit increment from 0 to 7 bits.
The LIDR0 to LIDR15 registers are configured as follows:
14.5.1
When SMPL_MODE = LOW, these five bits define the amount of input bit delay adjustment that the receiver uses to
sample each input. Input bit delay adjustment can range up to 7
period. The default sampling point is at the
This can be described as: no. of bits delay = LID[4:0] / 4
For example, if LID[4:0] is set to 10011 (19), the input bit delay = 19 *
When SMPL_MODE = HIGH, the binary value of LID[1:0] refers to the input bit sampling point (
refers to the integer bit delay value (0 to 7 bits). This means that bits can be delayed by an integer value of up to 7
and that the sampling point can vary from
Table 27 illustrates the bit delay and sampling point selection.
Non-32Mbps Mode, n = 0 to 7
(where n = 0 to 15 for Local
for Local 32Mbps Mode)
Local Input Bit Delay Registers (LIDR0 to LIDR15)
Local Input Delay Bits 4-0 (LID[4:0])
LIDRn Bit
LID4
0
15:5
4:0
H
Table 27 - Local Input Bit Delay and Sampling Point Programming Table
to 0032
LID3
3
/
0
4
bits, in steps of
H
.
Table 26 - Local Input Bit Delay Register (LIDRn) Bits
LIDn
LID2
0
Reserved
LID[4:0]
Name
1
LID1
/
4
0
1
bit.
/
3
4
/
4
to
Reset
Value
Zarlink Semiconductor Inc.
bit location.
4
0
0
ZL50057/8
/
4
LID0
in
0
1
/
Reserved
Must be set to 0 for normal operation
Local Input Bit Delay Register
When SMPL_MODE = LOW, the binary value of these
bits refers to the input bit and fractional bit delay value (0
to 7
When SMPL_MODE = HIGH, the binary value of LID[1:0]
refers to the input bit sampling point (
refers to the integer bit delay value (0 to 7 bits).
4
72
-bit increments.
SMPL_MODE
3
Input Data
0 (Default)
/
Bit Delay
4
= LOW
).
3
/
4
1
bit periods forward, with resolution of
/
4
= 4
3
Input Data
0 (Default)
Bit Delay
/
4
Description
.
SMPL_MODE
= HIGH
Input Data
1
Sampling
/
4
Point
to
1
3/4
/
4
4
to
/
4
Data Sheet
). LID[4:2]
4
/
4
). LID[4:2]
1
/
4
bit