zl50058 Zarlink Semiconductor, zl50058 Datasheet - Page 30

• Manufacturer Part Number: zl50058
• Description: 12 K Channel Digital Switch With High Jitter Tolerance, Per Stream Rate Conversion 2, 4, 8, 16 Or 32 Mbps , 48 Input And 48 Output Streams
• Manufacturer: Zarlink Semiconductor

3.1.1
By programming the Backplane or Local Input Channel Delay Registers (BCDR0 - BCDR31 and LCDR0 -
LCDR15), users can individually assign the Ch0 position of each input stream to be located at any of the channel
boundaries in a frame. For delays within channel boundaries, the input bit delay programming can be used.
By default, all input streams have a channel delay of zero such that Ch0 is the first channel that appears after the
frame boundary.
3.1.2
In addition to the Input Channel Delay programming, Input Bit Delay Registers LIDR0-15 and BIDR0-31 work in
conjunction with the SMPL_MODE bit in the Control Register to allow users to control input bit fractional delay as
well as input bit sample point selection for greater flexibility when designing switch matrices for high speed
operation.
When SMPL_MODE = LOW (input bit fractional delay mode), bits LID[4:0] and BID[4:0] in the LIDR0-15 and
BIDR0-31 registers respectively define the input bit fractional delay of the corresponding local and backplane
stream. The total delay can be up to 7 3/4 bits with a resolution of 1/4 bit at the selected data rate. When
SMPL_MODE = HIGH (sampling point select mode), bits LID[1:0] and BID[1:0] define the input bit sampling point of
the stream. The sampling point can be programmed at the 3/4, 4/4, 1/4 or 2/4 bit location to allow better tolerance
for input jitter. Bits LID[4:2] and BID[4:2] define the integer input bit delay, with a maximum value of 7 bits at a
resolution of 1 bit.
Refer to Figure 10 and Figure 11 for Input Bit Delay Timing at 16 Mbps and 8 Mbps data rates, respectively.
Refer to Figure 11 for Input Sampling Point Selection Timing at 8 Mbps data rates.
BSTi0-31/LSTi0-15
BSTi0-31/LSTi0-15
BSTi0-31/LSTi0-15
Channel Delay = 0
Channel Delay = 1
Channel Delay = 2
Input Channel Delay Programming (Backplane and Local Input Streams)
Input Bit Delay Programming (Backplane and Local Input Streams)
Figure 9 - Backplane and Local Input Channel Delay Timing Diagram (assuming 8 Mbps
(Default)
FP8i
C8i
3
3
3
2
2
2
1 0
1 0
1 0
7
7
7
6
Channel Delay,1
6
6
5
5
Ch 0
Ch127
5
Ch126
4
4
4
3
3
3
2
2
2
Channel Delay, 2
1 0
1 0
1 0
Zarlink Semiconductor Inc.
7
7
7
ZL50057/8
6
6
6
Ch 1
5
Ch 0
5
Ch127
5
4
4
4
operation)
3
3
3
30
2
2
2
1 0
1 0
1 0
7
6
5
Ch0
4
3
6
6
2
5
5
Ch126
Ch125
1 0
4
4
3
3
2
2
1 0
1 0
7
7
7
6
6
6
5
5
5
Ch127
Ch126
Ch125
4
4
4
3
3
3
2
2
2
1 0
1 0
1 0
Data Sheet
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