am45dl3208g Advanced Micro Devices, am45dl3208g Datasheet
am45dl3208g
Related parts for am45dl3208g
am45dl3208g Summary of contents
Page 1
... Am45DL3208G Data Sheet September 2003 The following document specifies Spansion memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig- inally developed the specification, these products will be offered to customers of both AMD and Fujitsu ...
Page 2
THIS PAGE LEFT INTENTIONALLY BLANK. ...
Page 3
... PRELIMINARY Am45DL3208G Stacked Multi-Chip Package (MCP) Flash Memory and SRAM 32 Megabit ( 8-Bit 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 8 Mbit ( 8-Bit/512 K x 16-Bit) Pseudo Static RAM DISTINCTIVE CHARACTERISTICS MCP Features Power supply voltage of 2.7 to 3.3 volt High performance — ...
Page 4
... The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly re- duced in both modes. Am45DL3208G March 12, 2004 ...
Page 5
... Figure 30. Pseudo SRAM Read Cycle........................................... 56 Write Cycle ............................................................................. 57 Figure 31. Pseudo SRAM Write Cycle—WE# Control ................... 57 Figure 32. Pseudo SRAM Write Cycle—CE1#s Control ................ 58 Figure 33. Pseudo SRAM Write Cycle— UB#s and LB#s Control.................................................................. 59 Flash Erase And Programming Performance . . 60 Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 60 Package Pin Capacitance Am45DL3208G vs. Frequency............................................ 39 3 ...
Page 6
... Flash Data Retention . . . . . . . . . . . . . . . . . . . . . . 60 SRAM Data Retention . . . . . . . . . . . . . . . . . . . . . . 61 Figure 34. CE1#s Controlled Data Retention Mode........................ 61 Figure 35. CE2s Controlled Data Retention Mode.......................... 61 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . FLB073—73-Ball Fine-Pitch Grid Array 8 x 11.6 mm ............. 62 Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 63 Am45DL3208G March 12, 2004 ...
Page 7
... CIOs March 12, 2004 Am45DL3208G Flash Memory RY/BY# 32 MBit Flash Memory DQ15 to DQ0 V s CCQ SS SSQ 8 MBit DQ15 to DQ0 CompactCell SRAM Am45DL3208G Pseudo SRAM DQ15 to DQ0 5 ...
Page 8
... COMMAND CE# REGISTER BYTE# WP#/ACC DQ15–DQ0 A20–A0 Mux OE# BYTE# Bank 1 Bank 1 Address X-Decoder Bank 2 Address Bank 2 X-Decoder Status Control X-Decoder Bank 3 Bank 3 Address X-Decoder Bank 4 Address Bank 4 Am45DL3208G DQ15–DQ0 Mux March 12, 2004 ...
Page 9
... DQ11 CIOs DQ5 DQ14 The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time. Am45DL3208G Flash only A10 NC Pseudo B10 SRAM only NC Shared D9 A15 F10 NC NC ...
Page 10
... PSRAM Power Supply Device Ground (Common Pin Not Connected Internally LOGIC SYMBOL 19 A18–A0 A20–A19, A-1 SA CE#f CE1#s CE2s OE# WE# WP#/ACC RESET# UB#s LB#s CIOf CIOs Am45DL3208G DQ15–DQ0 RY/BY# March 12, 2004 ...
Page 11
... Mbits Order Number Am45DL3208GT70I Am45DL3208GB70I Am45DL3208GT85I Am45DL3208GB85I needed to execute the command. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Tables inputs and control levels they require, and the resulting output ...
Page 12
... 9.0 ± 0 Don’t Care PSRAM Address Address In Data In and CE2s = V at the same time. IH the boot sectors protection will be removed. IH Am45DL3208G ; P SRAM Word Mode, CIOs = V IH WP#/ACC DQ7– (Note 4) DQ0 X H L/H D OUT X H (Note 4) ...
Page 13
... 9.0 ± 0 Don’t Care PSRAM Address Address In Data In and CE2s = V at the same time. IH the boot sectors protection will be removed. IH Am45DL3208G ; PSRAM Byte Mode, CIOs = UB#s WP#/ACC DQ7– RESET# (Note 3) (Note 4) DQ0 X H L/H ...
Page 14
... 9.0 ± 0 Don’t Care PSRAM Address Address In (for Flash Byte Mode, DQ15 = A-1 and CE2s = V at the same time. IH the boot sectors protection will be removed. IH Am45DL3208G ; PSRAM Word Mode, CIOs = V SS UB#s WP#/ACC DQ7– RESET# (Note 4) DQ0 X H L/H ...
Page 15
... To read array data from the outputs, the system must drive the CE#f and OE# pins to V control and selects the device. OE# is the output con- trol and gates array data to the output pins. WE# should remain at V Am45DL3208G ; PSRAM Byte Mode, CIOs = V IL UB#s WP#/ACC DQ7– ...
Page 16
... CC mode, but the standby current will be greater. The de- vice requires standard access time (t cess when the device is in either of these standby modes, before it is ready to read data. Am45DL3208G on this pin, the device auto- HH must not be asserted on HH shows how read and write cycles ...
Page 17
... Am45DL3208G ±0.3 V, the device SS f). If RESET# is CC4 ±0.3 V, the standby cur- SS (during Embedded Algorithms). The sys- (not during Embedded Algo- READY after the RE Figure 16 for the timing diagram ...
Page 18
... A20:A0 in word mode (BYTE#=V IL Am45DL3208G (x16) Address Range 098000h–09FFFFh 0A0000h–0A7FFFh 0A8000h–0AFFFFh 0B0000h–0B7FFFh 0B8000h–0BFFFFh 0C0000h–0C7FFFh 0C8000h–0CFFFFh 0D0000h–0D7FFFh 0D8000h–0DFFFFh 0E0000h–0E7FFFh 0E8000h– ...
Page 19
... Am45DL3208G (x8) (x16) Address Range Address Range 3FE000h–3FE0FFh 1F0000h–1FF07Fh (x8) (x16) Address Range 000000h–000FFFh 001000h–001FFFh 002000h–002FFFh 003000h–003FFFh 004000h–004FFFh 005000h–005FFFh 006000h– ...
Page 20
... A20:A0 in word mode (BYTE#=V IL Bottom Boot SecSi¥ Sector Addresses Sector Address Sector Size A20–A12 (Bytes/Words) 000000xxx 256/128 Am45DL3208G (x16) Address Range 100000h–107FFFh 108000h–10FFFFh 110000h–117FFFh 118000h–11FFFFh 120000h–127FFFh 128000h–12FFFFh 130000h–137FFFh 138000h–13FFFFh 140000h– ...
Page 21
... This method uses standard microprocessor bus cycle timing. For sector unprotect, all unprotected sectors must first be protected prior to the first sector unprotect write cycle. Note that the sector unprotect algorithm unprotects all sectors in parallel. All previ- Am45DL3208G Sector/Sector Block A20–A12 Size 111111XXX ...
Page 22
... All protected sectors unprotected (If WP#/ACC = V sectors 0 and 1 (bottom boot and 70 (top boot) will remain protected). 2. All previously protected sectors are protected once again. Figure 1. Temporary Sector Unprotect Operation Am45DL3208G Table is removed from the RE- ID Figure 1 shows the algorithm, and ...
Page 23
... Reset PLSCNT = 1 Increment PLSCNT No Yes PLSCNT = 1000? Yes Device failed Sector Unprotect Algorithm Am45DL3208G START PLSCNT = 1 RESET Wait 1 µs No First Write Temporary Sector Cycle = 60h? Unprotect Mode Yes No All sectors protected? Yes ...
Page 24
... The SecSi Sector lock must be used with caution since, once locked, there is no procedure available for unlocking the SecSi Sector area and none of the bits in the SecSi Sector memory space can be modified in any way. Am45DL3208G Figure 2, ex This IH ...
Page 25
... For further information, please refer to the CFI Specifi- LKO cation and CFI Publication 100, available via the World is Wide Web at http://www.amd.com/flash/cfi. Alterna- CC tively, contact an AMD representative for copies of these documents. Am45DL3208G or WE initiate a write cycle and OE during power up, IL ...
Page 26
... Query Unique ASCII string “QRY” 0059h 0002h Primary OEM Command Set 0000h 0040h Address for Primary Extended Table 0000h 0000h Alternate OEM Command Set (00h = none exists) 0000h 0000h Address for Alternate OEM Extended Table (00h = none exists) 0000h Am45DL3208G Description March 12, 2004 ...
Page 27
... Erase Block Region 3 Information 0000h (refer to the CFI specification or CFI publication 100) 0000h 0000h 0000h Erase Block Region 4 Information 0000h (refer to the CFI specification or CFI publication 100) 0000h Am45DL3208G Description pin present) PP pin present µs µ (00h = not supported) ...
Page 28
... Not Supported Word Page Word Page ACC (Acceleration) Supply Minimum 0085h 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV ACC (Acceleration) Supply Maximum 0095h 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV Top/Bottom Boot Sector Flag 000xh 02h = Bottom Boot Device, 03h = Top Boot Device Am45DL3208G Description March 12, 2004 ...
Page 29
... Erase Suspend). Enter SecSi™ Sector/Exit SecSi Sector Command Sequence The SecSi Sector region provides a secured data area containing a random, sixteen-byte electronic serial number (ESN). The system can access the SecSi Am45DL3208G show the address and data require- 5 and 7 show ...
Page 30
... In addition, the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may resul t. Figure 4 illustrates the algorithm for the program oper- ation. Refer to the Flash Erase and Program Opera- tions table in the AC Characteristics section for parameters, and Am45DL3208G 15 and 16 show the re- any operation HH Figure 19 for timing diagrams ...
Page 31
... DQ3: Sector Erase Timer.). The time-out begins from the ris- ing edge of the final WE# pulse in the command sequence. When the Embedded Erase algorithm is complete, the bank returns to reading array data and addresses are Am45DL3208G section for timing diagrams. 15 and 16 show the ...
Page 32
... Data Poll to Erasing Bank from System No Data = FFh? Erasure Completed Notes: 1. See Tables 15 and 2. See the section on DQ3 for information on the sector erase timer. Figure 5. Erase Operation Am45DL3208G START Embedded Erase algorithm in progress Yes 16 for erase command sequence. March 12, 2004 ...
Page 33
... The Erase Resume command is valid only during the Erase Suspend mode, and requires the bank address. 16. Command is valid when device is ready to read array data or when device is in autoselect mode. Am45DL3208G Fourth Fifth Data Addr Data ...
Page 34
... The Erase Resume command is valid only during the Erase Suspend mode, and requires the bank address. 16. Command is valid when device is ready to read array data or when device is in autoselect mode. Am45DL3208G Fourth Fifth Sixth Addr Data ...
Page 35
... During chip erase, a valid address is any non-protected sector address. 2. DQ7 should be rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5. Figure 6. Data# Polling Algorithm Am45DL3208G Figure 23 Yes No Yes Yes ...
Page 36
... Note: The system should recheck the toggle bit even if DQ5 = “1” because the toggle bit may stop toggling as DQ5 changes to “1.” See the subsections on DQ6 and DQ2 for more information. Figure 7. Toggle Bit Algorithm Am45DL3208G Figure 24 in Figure 25 shows the differ- ...
Page 37
... DQ3 prior to and following each subsequent sector erase com- mand. If DQ3 is high on the second status check, the last command might not have been accepted. Table 17 shows the status of DQ3 relative to the other status bits. Am45DL3208G Figure 7). 35 ...
Page 38
... The device outputs array data if the system addresses a non-busy bank Table 17. Write Operation Status DQ7 DQ5 (Note 2) DQ6 (Note 1) DQ7# Toggle 0 Toggle 1 No toggle Data Data Data DQ7# Toggle Am45DL3208G DQ2 DQ3 (Note 2) RY/BY# 0 N/A No toggle Toggle 0 0 N/A Toggle 1 Data Data 1 ...
Page 39
... March 12, 2004 +0.8 V –0.5 V –2 –2.0 V for SS 2 Maximum DC input Am45DL3208G Figure 8. Maximum Negative Overshoot Waveform Figure 9. Maximum Positive Overshoot Waveform 37 ...
Page 40
... CC CC min I = –100 µ min 4. Automatic sleep mode enables the low power mode when addresses remain stable for t current is 200 nA max Not 100% tested. Am45DL3208G Min Typ Max Unit µA ±1.0 35 µA 35 µA µA ±1.0 35 µ ...
Page 41
... Current vs. Time (Showing Active and Automatic Sleep Currents) CC1 Note ° C March 12, 2004 1000 1500 2000 Time Frequency in MHz Figure 11. Typical I vs. Frequency CC1 Am45DL3208G 2500 3000 3500 3 4000 39 ...
Page 42
... OH CE1 CE2 = V , Other IH IL inputs = CE1#s ≥ V – 0.2 V, CE2 ≥ 0.2 V (CE1#s controlled) or CE2 ≤ 0.2 V (CE2s controlled), CIOs = Other input = ns. Am45DL3208G Min Typ Max –1.0 1.0 –1.0 1 –0.2 0.4 (Note 3) V +0.2 CC 2.2 (Note 2) 0.4 2 ...
Page 43
... Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels Output timing measurement reference levels INPUTS Steady Changing from Changing from Does Not Apply Center Line is High Impedance State (High Z) Measurement Level Am45DL3208G 70, 85 Unit 1 TTL gate 0.0–3 ...
Page 44
... Parameter JEDEC Std Description — t CE#s Recover Time CCR CE#f CE1#s CE2s Figure 14. Timing Diagram for Alternating CCR t CCR Between Pseudo SRAM and Flash Am45DL3208G Test Setup All Speeds Unit — Min 0 t CCR t CCR March 12, 2004 ns ...
Page 45
... Test Setup CE# Read Toggle and Data# Polling Addresses Stable t ACC OEH t CE HIGH Z Output Valid Figure 15. Read Operation Timings Am45DL3208G Speed 70 85 Unit Min 70 85 Max Max Max 30 40 Max 16 16 Max 16 ...
Page 46
... Description Max Max Min Min Min Min Ready Reset Timings NOT during Embedded Algorithms Reset Timings during Embedded Algorithms t Ready t RP Figure 16. Reset Timings Am45DL3208G All Speed Options Unit 20 µs 500 ns 500 µ March 12, 2004 ...
Page 47
... FLQZ t ELFH Data Output (DQ7–DQ0) Address DQ15 Input Output t FHQV The falling edge of the last WE# signal t SET ( HOLD AH and t specifications Am45DL3208G Speed 70 85 Unit Data Output (DQ7–DQ0) Address Input Data Output (DQ14–DQ0) 45 ...
Page 48
... Notes: 1. Not 100% tested. 2. See the “Flash Erase And Programming Performance” section for more information CE#f Low During Toggle Bit Read Toggle and Data# Polling Byte Word Am45DL3208G Speed Options Unit 70 85 Min Min 0 ...
Page 49
... WPH A0h t BUSY is the true data at the program address. OUT Figure 19. Program Operation Timings Am45DL3208G Read Status Data (last two cycles WHWH1 D Status OUT VHH 47 ...
Page 50
... These waveforms are for the word mode. Figure 21. Chip/Sector Erase Operation Timings SADD 555h for chip erase WPH t DH 55h 30h 10 for Chip Erase t BUSY Am45DL3208G Read Status Data WHWH2 In Complete Progress t RB March 12, 2004 ...
Page 51
... OEH GHWL Valid Out t SR/W Read Cycle Complement Complement Status Data Status Data Am45DL3208G Valid PA Valid PA t CPH t CP Valid Valid In In CE#f Controlled Write Cycles VA High Z Valid Data True High Z True Valid Data 49 ...
Page 52
... AHT t ASO t CEPH t OEPH t OE Valid Valid Status Status (first read) (second read) Enter Erase Suspend Program Erase Erase Suspend Suspend Read Program Figure 25. DQ2 vs. DQ6 Am45DL3208G Valid Valid Data Status (stops toggling) Erase Resume Erase Erase Complete Read March 12, 2004 ...
Page 53
... VIDR CE#f WE# RY/BY# Figure 26. Temporary Sector Unprotect Timing Diagram March 12, 2004 Min Min Min Min Program or Erase Command Sequence t RSP Am45DL3208G All Speed Options Unit 500 ns 250 ns 4 µs 4 µ ...
Page 54
... For sector protect For sector unprotect SADD = Sector Address. Figure 27. Sector/Sector Block Protect and Valid* Valid* 60h Sector/Sector Block Protect: 150 µs, Sector/Sector Block Unprotect Unprotect Timing Diagram Am45DL3208G Valid* Verify 40h Status March 12, 2004 ...
Page 55
... Sector Erase Operation (Note 2) WHWH2 WHWH2 Notes: 1. Not 100% tested. 2. See the “Flash Erase And Programming Performance” section for more information. March 12, 2004 Byte Word Am45DL3208G Speed 70 85 Unit Min Min 0 ns Min ...
Page 56
... SADD for sector erase 555 for chip erase Data# Polling GHEL t t WHWH1 CPH t BUSY for program PD for program 55 for erase 30 for sector erase 10 for chip erase is the data written to the device. OUT Am45DL3208G PA DQ7# D OUT March 12, 2004 ...
Page 57
... CE# Min Max Max Max Max Min Min Min Max Max Max Min UB#s and/or LB for continuous periods < 10 µs. RC Am45DL3208G . IH Speed Unit ...
Page 58
... CO1 t CO2 OLZ t BLZ t LZ (Max.) is less than t (Min.) both for a given device and from device to device HZ LZ for continuous periods < 10 µs. RC Figure 30. Pseudo SRAM Read Cycle Am45DL3208G OHZ Data Valid March 12, 2004 ...
Page 59
... WP (See Note (See Note 3) High-Z t WHZ Data Undefined applied in case a write ends as CE1#s or WE# going high low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when Am45DL3208G Speed Unit ...
Page 60
... (See Note 5) High-Z applied in case a write ends as CE1#s or WE# going high low CE1#s and low WE#. A write begins when CE1#s goes low and WE# goes low when Am45DL3208G t (See Note Data Valid High-Z is measured from the beginning of write ...
Page 61
... Note 5) t High-Z applied in case a write ends as CE1#s or WE# going high low CE#1s and low WE#. A write begins when CE1#s goes low and WE# goes low when Figure 33. Pseudo SRAM Write Cycle— UB#s and LB#s Control Am45DL3208G t (See Note Data Valid ...
Page 62
... V, 1,000,000 cycles 3.0 V, one pin at a time. CC Test Setup V V OUT V V Test Conditions Am45DL3208G Unit Comments sec Excludes 00h programming prior to erasure (Note 4) sec µs µs Excludes system level µs overhead (Note 5) sec , 1,000,000 cycles. Additionally, CC Min Max – ...
Page 63
... CS1#s ≥ V – 0.2 V (Note 3.0 V, CE1#s ≥ V – 0 (Note 1) See data retention waveforms Data Retention Mode t SDR CE1 0.2 V ≥ CC Data Retention Mode t SDR CE2s < 0.2 V Am45DL3208G Min Typ Max Unit 2.7 3.3 V 1.0 100 µA (Note ...
Page 64
... PHYSICAL DIMENSIONS FLB073—73-Ball Fine-Pitch Grid Array Am45DL3208G March 12, 2004 ...
Page 65
... Noted that the SecSi Sector, autoselect, and CFI functions are unavailable when a program or erase operation is in progress. Common Flash Memory Interface (CFI) Changed CFI website address. Revision B+1 (March 12, 2004) Table 15. Command Definitions (Flash Word Mode) In Note 9, changed device ID for top boot to 01h and for bottom boot to 00h. Am45DL3208G 63 ...
Page 66
... Frimley . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Haydock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Advanced Micro Devices reserves the right to make changes in its product without notice in order to improve design or performance characteristics.The performance characteristics listed in this document are guaranteed by specific tests, guard banding, design and other practices common to the industry ...