am45dl3208g Advanced Micro Devices, am45dl3208g Datasheet - Page 31

• Manufacturer Part Number: am45dl3208g
• Description: Stacked Multi-chip Package Mcp Flash Memory And Sram
• Manufacturer: Advanced Micro Devices

Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does not require the system to
preprogram prior to erase. The Embedded Erase algo-
rithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any con-
trols or timings during these operations. Tables
16
chip erase command sequence.
When the Embedded Erase algorithm is complete,
that bank returns to the read mode and addresses are
no longer latched. The system can determine the sta-
tus of the erase operation by using DQ7, DQ6, DQ2,
or RY/BY#. Refer to the Flash Write Operation Status
section for information on these status bits.
March 12, 2004
Note: See Tables
sequence.
show the address and data requirements for the
Increment Address
Figure 4. Program Operation
Embedded
in progress
15
algorithm
Program
and
16
No
for program command
Command Sequence
Write Program
Last Address?
Programming
from System
Verify Data?
Completed
Data Poll
START
Yes
Yes
P R E L I M I N A R Y
15
No
Am45DL3208G
and
Any commands written during the chip erase operation
are ignored. However, note that a hardware reset im-
mediately terminates the erase operation. If that oc-
curs, the chip erase command sequence should be
reinitiated once that bank has returned to reading
array data, to ensure data integrity. Note that the
SecSi Sector, autoselect, and CFI functions are un-
available when an erase operation in is progress.
Figure 5
tion. Refer to the Flash Erase and Program Operations
tables in the AC Characteristics section for parame-
ters, and
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two ad-
ditional unlock cycles are written, and are then fol-
lowed by the address of the sector to be erased, and
the sector erase command. Tables
address and data requirements for the sector erase
command sequence.
The device does not require the system to preprogram
prior to erase. The Embedded Erase algorithm auto-
matically programs and verifies the entire memory for
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or tim-
ings during these operations.
After the command sequence is written, a sector erase
time-out of 80 µs occurs. During the time-out period,
additional sector addresses and sector erase com-
mands may be written. Loading the sector erase buffer
may be done in any sequence, and the number of sec-
tors may be from one sector to all sectors. The time
between these additional cycles must be less than 80
µs, otherwise erasure may begin. Any sector erase ad-
dress and command following the exceeded time-out
may or may not be accepted. It is recommended that
processor interrupts be disabled during this time to en-
sure all commands are accepted. The interrupts can
be re-enabled after the last Sector Erase command is
written. Any command other than Sector Erase or
Erase Suspend during the time-out period resets
that bank to the read mode. The system must rewrite
the command sequence and any additional addresses
and commands. Note that the SecSi Sector, autose-
lect, and CFI functions are unavailable when an erase
operation in is progress.
The system can monitor DQ3 to determine if the sec-
tor erase timer has timed out (See the section on DQ3:
Sector Erase Timer.). The time-out begins from the ris-
ing edge of the final WE# pulse in the command
sequence.
When the Embedded Erase algorithm is complete, the
bank returns to reading array data and addresses are
illustrates the algorithm for the erase opera-
Figure 21
section for timing diagrams.
15
and
16
show the
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