tmpr4937 TOSHIBA Semiconductor CORPORATION, tmpr4937 Datasheet - Page 122

• Manufacturer Part Number: tmpr4937
• Description: 64-bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

17:16
15:12
11:8
Bit
7
Mnemonic
PWT
WT
CS
BC
Page Mode
Wait time
Normal Mode
Wait Time
Channel Size
Byte Control
Field Name
Figure 7.4.1 External Bus Channel Control Register (2/3)
External Bus Control Page Mode Wait Time (Default: 11 / 00)
Specifies the wait cycle count during Burst access when in the Page mode.
00: 0 wait cycles
01: 1 wait cycle
Specifies a wait cycle count from 0 to 62 that matches WT when in the
Normal mode or Ready mode. (See the WT item.)
External Bus Control Normal Mode Wait Time
(Default: 111 (~DATA[4])/0000)
Specifies the wait cycle count in the first cycle of a Single Cycle or Burst
access.
Specifies the following wait cycle count when in the Page mode.
0000: 0 wait cycles
1000: 8 wait cycles
0001: 1 wait cycle
1001: 9 wait cycles
0010: 2 wait cycles
1010: 10 wait cycles
0011: 3 wait cycles
1011: 11 wait cycles
Specifies a wait cycle count from 0 to 62 that matches PWT when in a mode
other than the Page mode.
PWT[1:0]: WT[3:0]
000000: 0 wait cycles
000001: 1 wait cycle
001110: 14 wait cycles 011110: 30 wait cycles 111110: 62 wait cycles
001111: 15 wait cycles 011111: 31 wait cycles 111111: External ACK mode
Note 1: Value that is the reverse of DATA[4] is set to the LSB of Channel 0
Note 2: If PWT:WT is set to 0x3f when PM = 00 and RDY = 0, the external
Note 3: WT[0] is used to select Dynamic/Static ACK*/Ready mode when in
Note 4: The WT wait cycle count should be equal to or greater than the
External Bus Control Channel Size (Default: 0010/0000)
Specifies the channel memory size.
0000: 1 MB
0001: 2 MB
0010: 4 MB
0011: 8 MB
0100: 16 MB
* The channel memory size can be set up to 512 MB when the memory bus
External Bus Byte Control (Default: DATA[5]/0)
Specifies whether to use the BWE*[3:0] signal as an asserted Byte Write
Enable signal (BWE*[3:0]) only during a Write cycle, or to use it as an
asserted Byte Enable signal (BE*[3:0]) that is asserted during both Read
and Write cycles.
0: Byte Enable (BE *[3:0])
1: Byte Write Enable (BWE*[3:0])
Note: DATA[5] is set to Channel 0 as the default.
width is 16 bits, or up to 256 MB when the memory bus width is 8 bits. No
size larger than this can be set.
as the default.
bus enters the ACK* Input mode (External ACK mode) without the
wait cycle count for the ACK* output being the maximum value.
the Ready mode. Therefore, the Wait cycle count is an even
number.
PWT Wait cycle count when in the Page mode.
:
7-22
10: 2 wait cycles
11: 3 wait cycles
0101: 32 MB
0110: 64 MB
0111: 128 MB
1000: 256 MB
1001: 512 MB
0100: 4 wait cycles
1100: 12 wait cycles
0101: 5 wait cycles
1101: 13 wait cycles
0110: 6 wait cycles
1110: 14 wait cycles
0111: 7 wait cycles
1111: 15 wait cycles
010000: 16 wait cycles 110000: 48 wait cycles
010001: 17 wait cycles 110001: 49 wait cycles
Chapter 7 External Bus Controller
Description
:
*1010: 1 GB
1011-1111: Reserved
:
Read/Write
R/W
R/W
R/W
R/W