tmpr4937 TOSHIBA Semiconductor CORPORATION, tmpr4937 Datasheet - Page 56

• Manufacturer Part Number: tmpr4937
• Description: 64-bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Signal Name
SDCLK[3:0]
SDCLKIN
CKE
SDCS[3:0]*
RAS*
CAS*
WE*
DQM[7:0]
CB[7:0]
3.1.2
SDRAM Interface Signals
Input/output SDRAM Feedback Clock input
Input/output
Output
Output
Output
Output
Output
Output
Output
Type
PU
SDRAM Controller Clock
Clock signals used by SDRAM. The clock frequency is the same as the G-Bus clock
(GBUSCLK) frequency.
When these clock signals are not used, the pins can be set to H using the SDCLK
Enable field of the configuration register (CCFG.SDCLKEN[3:0]).
Feedback clock signal for SDRAM controller input signals.
Setting the SDCLKINEN bit of the pin configuration register causes the TX4937 to
feed back signals internally, making SDCLKIN an output signal.
Clock Enable
CKE signal for SDRAM.
Synchronous Memory Device Chip Select
Chip select signals for SDRAM.
Row Address Strobe
RAS signal for SDRAM.
Column Address Strobe
CAS signal for SDRAM.
Write Enable
WR signal for SDRAM.
Data Mask
During a write cycle, the DQM signals function as a data mask. During a read cycle,
they control the SDRAM output buffers. The bits correspond to the following data bus
signals:
DQM[7]:DATA[63:54], DQM[6]:DATA[53:48]
DQM[5]:DATA[47:40], DQM[4]:DATA[39:32]
DQM[3]:DATA[31:24], DQM[2]:DATA[23:16]
DQM[1]:DATA[15:8],
Connect any one of the DQM[3:0] to SDRAM which connects CB.
ECC/Parity Check Bit
ECC/parity check bit signals. The bits correspond to the following data bus signals:
CB[7]:DATA[63:54],
CB[5]:DATA[47:40],
CB[3]:DATA[31:24],
CB[1]:DATA[15:8],
CB[7:0] share pins with other function signals (refer to Section “3.3 Pin multiplex”).
Table 3.1.2 SDRAM Interface Signals
DQM[0]:DATA[7:0]
CB[6]:DATA[53:48]
CB[4]:DATA[39:32]
CB[2]:DATA[23:16]
CB[0]:DATA[7:0]
3-2
Description
Chapter 3 Signals
Initial State
All High
Input
High
All High
High
High
High
All High
Input