tmpr4937 TOSHIBA Semiconductor CORPORATION, tmpr4937 Datasheet - Page 171

• Manufacturer Part Number: tmpr4937
• Description: 64-bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

8.3.8.3
the Destination Address is divided into multiple 8-byte Single Write transfers, then transfer is
executed.
accesses to an external I/O device, a Single transfer is divided into multiple accesses, depending
on its bus width. Thus, the address changes during a Single transfer. For more on this, see Section
7.3.5, "Data Bus Size." To continually access a fixed address in an external I/O device, program
the trasnfer size (DMCCRn.XFSZ) to the bus width of the I/O device and perform Single transfers
with the Burst Inhibit bit cleared.
Double Word Byte Swapping
(DMCCRn) is set, read double word data is written after byte swapping is performed. For
example, if the read data is “0x01234567_90ABCDEF”, then the data “0xEFCDAB89_67452301”
is written.
is indicated.
When the Destination Burst Inhibit bit (DMCCRn.DBINH) is set, data written from the FIFO to
When the Burst Inhibit bit is set, the TX4937 always performs an 8-byte Single transfer. For
When the Reverse Byte bit (REVBYTE) of the DMA Channel Configuration Register
The Reverse Byte bit can only be set when the REVBYTE column of Table 8.3.3 is set so “0/1”
8-15
Chapter 8 DMA Controller