tmpr4937 TOSHIBA Semiconductor CORPORATION, tmpr4937 Datasheet - Page 223
tmpr4937
Manufacturer Part Number
tmpr4937
Description
64-bit Tx System Risc
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet
1.TMPR4937.pdf
(552 pages)
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Row Address Width = 11
Column Address Width = 8
Address Bit
ADDR [19:5]
Column
Address
Row Address
Row Address Width = 11
Column Address Width = 9
Address Bit
ADDR [19:5]
Column
Address
Row Address
Row Address Width = 11
Column Address Width = 10
Address Bit
ADDR [19:5]
Column
Address
Row Address
Row Address Width = 12
Column Address Width = 8
Address Bit
ADDR [19:5]
Column
Address
Row Address
Row Address Width = 12
Column Address Width = 9
Address Bit
ADDR [19:5]
Column
Address
Row Address
Row Address Width = 12
Column Address Width = 10
Address Bit
ADDR [19:5]
Column
Address
Row Address
9.3.2.3
(B0)
(B0)
(B0)
(B0)
(B0)
(B0)
Address Signal Mapping (32-bit Data Bus)
bank selection in memory with a two-bank configuration. [B1:B0] are used in the bank selection
in memory with a four-bank configuration. Bits with the description "L/H" output High when
performing auto-precharging, or output Low when not performing auto-precharging.
19
21
21
19
22
22
19
23
23
19
22
22
19
23
23
19
24
24
Table 9.3.3 shows the address signal mapping when using a 32-bit data bus. B0 is used in the
Table 9.3.3 Address Signal Mapping (32-bit Data Bus) (1/2)
(B1)
(B1)
(B1)
(B1)
(B1)
(B1)
18
22
22
18
22
22
18
22
22
18
23
23
18
24
24
18
25
25
17
20
20
17
22
22
17
22
22
17
22
22
17
23
23
17
24
24
16
19
19
16
22
22
16
23
23
16
21
21
16
21
21
16
21
21
(AP)
(AP)
(AP)
(AP)
(AP)
(AP)
L/H
L/H
L/H
L/H
L/H
L/H
15
20
15
20
15
20
15
20
15
20
15
20
L/H
14
19
14
22
19
14
22
19
14
23
19
14
23
19
14
23
19
9-7
L/H
13
18
13
21
18
13
21
18
13
22
18
13
22
18
13
22
18
12
17
12
17
12
17
12
17
12
17
12
17
9
9
9
9
9
9
Chapter 9 SDRAM Controller
11
16
11
16
11
16
11
16
11
16
11
16
8
8
8
8
8
8
10
15
10
15
10
15
10
15
10
15
10
15
7
7
7
7
7
7
14
14
14
14
14
14
9
6
9
6
9
6
9
6
9
6
9
6
13
13
13
13
13
13
8
5
8
5
8
5
8
5
8
5
8
5
12
12
12
12
12
12
7
4
7
4
7
4
7
4
7
4
7
4
11
11
11
11
11
11
6
3
6
3
6
3
6
3
6
3
6
3
10
10
10
10
10
10
5
2
5
2
5
2
5
2
5
2
5
2
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