tmpr4937 TOSHIBA Semiconductor CORPORATION, tmpr4937 Datasheet - Page 89

• Manufacturer Part Number: tmpr4937
• Description: 64-bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Bit
7:4
1:0
8
3
2
1
Mnemonic
DMASEL3
DMASEL2
DMASEL1
DMASEL0
SEL1
⎯
Shared-Pin
Status 1
Reserved
DMA Request
Select 3
DMA Request
Select 2
DMA Request
Select 1
DMA Request
Select 0
Field Name
Figure 5.2.3 Pin Configuration Register (3/3)
Indicates which function, PIO[15:8] or CB[7:0], the shared pins
are set to.
L: 0 = The shared pins are set to PIO[15:8].
H: 1 = The shared pins are set to CB[7:0].
Selects a DMA request used by DMA controller 0 channel 3.
0: DMAREQ[3] (external)
1: SIO channel 0 transmission (internal)
Selects a DMA request used by DMA controller 0 channel 2.
0: DMAREQ[2] (external)
1: SIO channel 0 reception (internal)
Selects a DMA request used by DMA controller 0 channel 1.
00: DMAREQ[1] (external)
01: SIO channel 1 transmission (internal)
Selects a DMA request used by DMA controller 0 channel 0.
00: DMAREQ[0] (external)
01: SIO channel 1 reception (internal)
5-9
Description
⎯
Chapter 5 Configuration Registers
Initial Value Read/Write
ADDR[18]
0
0
0
0
⎯
R
R/W
R/W
R/W
R/W
⎯