tmpr4937 TOSHIBA Semiconductor CORPORATION, tmpr4937 Datasheet - Page 518

• Manufacturer Part Number: tmpr4937
• Description: 64-bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

INT Input Pulse Width Time
NMI Input Pulse Width Time
Notes:
21.5.9
SDCLK[n]
DMAACK[n]
(1) DMAREQ[n]
(2) DMAACK[n]
(3) DMADONE*
Edge Detection: Set the pulse width to 1.1× the GBUSCLK cycle or higher.
Level Detection: There is no AC characteristic definition. Continue asserting DMAREQ[3:0]
The DMAACK[n] signal is synchronous to SDCLK. (It is driven by GUBSCLK inside the chip.
See Chapter 6 for more information.)
The DMAACK[n] signal is asserted by SYSCLK or SDCLK for 3 cycles or more. However, this
is changed by the conditions [1] and [2] below.
[1] DMAC transfer mode (Single Address transfer, Dual Address transfer)
[2] Access time of the device DMAC accesses
•
•
Is asserted for only 1 SYSCLK cycle synchronous to SYSCLK.
Interrupt Interface AC characteristics
Item
When driving an external device with SYSCLK
Is asserted by SYSCLK for at least 3 cycles even in the shortest assertion case.
When driving an external device with SDCLK
Is asserted by SDCLK for at least 3 cycles even in the shortest assertion case. The AC
characteristics for Single Address transfer with SDRAM are tight, so we do not
recommend Single Address transfer.
Figure 21.5.10 Timing Diagram: INT/NMI Interface
until DMAACK[3:0] is received.
t
t
(Tc = 0 – 70°C, V
PW_INT
PW_NMI
Symbol
t
PW_INT
Boot configuration
ADDR[2]=H
Boot configuration
ADDR[2]=L
Boot configuration
ADDR[2]=H
Boot configuration
ADDR[2]=L
21-12
CCIO
/t
PW_NMI
Conditions
Chapter 21 Electrical Characteristics
= 3.3 V ± 0.2 V, V
Assertion Time
CCInt
1/2 × t
1/4 × t
2 × t
t
MCP
MCP
Min.
MCP
MCP
= 1.5 V ± 0.1 V, V
× 1.1
× 1.1
× 1.1
× 1.1
Max.
⎯
⎯
⎯
⎯
SS
= 0 V)
Unit
ns
ns
ns
ns