h5tq4g43mmr Hynix Semiconductor, h5tq4g43mmr Datasheet - Page 12

• Manufacturer Part Number: h5tq4g43mmr
• Description: 4gb Ddr3 Sdram Ddp
• Manufacturer: Hynix Semiconductor

Rev. 0.1 /Aug 2008
Notes:
1. All DDR3 SDRAM commands are defined by states of CS, RAS, CAS, WE and CKE at the rising edge of the
2. RESET is Low enable command which will be used only for asynchronous reset so must be maintained HIGH during
3. Bank addresses (BA) determine which bank is to be operated upon. For (E)MRS BA selects an (Extended) Mode
4. “V” means “H or L (but a defined logic level)” and “X” means either “defined or undefined (like floating) logic level”.
5. Burst reads or writes cannot be terminated or interrupted and Fixed/on the Fly BL will be defined by MRS.
6. The Power Down Mode does not perform any refresh operation.
7. The state of ODT does not affect the states described in this table. The ODT function is not available during Self
8. Self Refresh Exit is asynchronous.
9. VREF (Both VrefDQ and VrefCA) must be maintained during Self Refresh operation.
10. The No Operation command should be used in cases when the DDR3 SDRAM is in an idle or wait state. The purpose
11. The Deselect command performs the same function as No Operation command.
12. Refer to the CKE Truth Table for more detail with CKE transition.
any function.
Register.
ZQ Calibration Short
ZQ Calibration Long
clock. The MSB of BA, RA and CA are device density and configuration dependant.
Refresh.
of the No Operation command (NOP) is to prevent the DDR3 SDRAM from registering any unwanted commands
between operations. A No Operation command will not terminate a previous operation that is still executing, such as
a burst read or write cycle.
Power Down Exit
Function
Abbrev
ZQCS
iation
ZQCL
PDX
Cycle
Previ
ous
H
H
L
CKE
Curre
Cycle
nt
H
H
H
CS
H
L
L
L
RAS
H
V
H
H
CAS
H
V
H
H
WE
H
V
L
L
BA0-
BA3
V
X
X
A13-
A15
X
V
X
H5TQ4G43MMR-xxC
H5TQ4G83MMR-xxC
A12-
BC
V
X
X
A10-
AP
H
V
L
A11
A0-
A9,
V
X
X
12
Notes
6,12