h5tq4g43mmr Hynix Semiconductor, h5tq4g43mmr Datasheet - Page 40

• Manufacturer Part Number: h5tq4g43mmr
• Description: 4gb Ddr3 Sdram Ddp
• Manufacturer: Hynix Semiconductor

Rev. 0.1 /Aug 2008
I
I
I
I
I
DD6ET
DD6TC
DD4W
I
DD4R
DD5B
DD6
Operating Burst Read Current
CKE: High; External clock: On; tCK, CL: see Table 1 on page 38; BL: 8
mand, Address, Bank Address Inputs: partially toggling according to Table 7 on page 44; Data IO: seamless
read data burst with different data between one burst and the next one according to Table 7 on page 44; DM:
stable at 0; Bank Activity: all banks open, RD commands cycling through banks: 0,0,1,1,2,2,...(see Table 7 on
page 44); Output Buffer and RTT: Enabled in Mode Registers
Table 7 on page 44
Operating Burst Write Current
CKE: High; External clock: On; tCK, CL: see Table 1 on page 38; BL: 8
mand, Address, Bank Address Inputs: partially toggling according to Table 8 on page 44; Data IO: seamless
read data burst with different data between one burst and the next one according to Table 8 on page 44; DM:
stable at 0; Bank Activity: all banks open, WR commands cycling through banks: 0,0,1,1,2,2,...(see Table 8 on
page 44); Output Buffer and RTT: Enabled in Mode Registers
see Table 8 on page 44
Burst Refresh Current
CKE: High; External clock: On; tCK, CL, nRFC: see Table 1 on page 38; BL: 8
Command, Address, Bank Address Inputs: partially toggling according to Table 9 on page 45; Data IO: FLOAT-
ING; DM: stable at 0; Bank Activity: REF command every nREF (see Table 9 on page 45); Output Buffer and
RTT: Enabled in Mode Registers
Self-Refresh Current: Normal Temperature Range
T
CKE: Low; External clock: Off; CK and CK: LOW; CL: see Table 1 on page 38; BL: 8
Address, Bank Address Inputs, Data IO: FLOATING; DM: stable at 0; Bank Activity: Self-Refresh operation;
Output Buffer and RTT: Enabled in Mode Registers
Self-Refresh Current: Extended Temperature Range (optional)
T
CKE: Low; External clock: Off; CK and CK: LOW; CL: see Table 1 on page 38; BL: 8
Address, Bank Address Inputs, Data IO: FLOATING; DM: stable at 0; Bank Activity: Extended Temperature
Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers
Auto Self-Refresh Current (optional)
T
Low; External clock: Off; CK and CK: LOW; CL: see Table 1 on page 38; BL: 8
Address, Bank Address Inputs, Data IO: FLOATING; DM: stable at 0; Bank Activity: Auto Self-Refresh opera-
tion; Output Buffer and RTT: Enabled in Mode Registers
CASE
CASE
CASE
: 0 - 85
: 0 - 95
: 0 - 95
o
o
o
C; Auto Self-Refresh (ASR): Enabled
C; Auto Self-Refresh (ASR): Disabled
C; Auto Self-Refresh (ASR): Disabled
b)
; ODT Signal: stable at 0; Pattern Details: see Table 9 on page 45
f)
b)
d)
d)
d)
; ODT Signal: FLOATING
;Self-Refresh Temperature Range (SRT): Normal
;Self-Refresh Temperature Range (SRT): Normal
;Self-Refresh Temperature Range (SRT): Extended
b)
; ODT Signal: FLOATING
b)
b)
f)
; ODT Signal: stable at 0; Pattern Details: see
; ODT Signal: stable at HIGH; Pattern Details:
a)
a)
; AL: 0; CS: High between RD; Com-
; AL: 0; CS: High between WR; Com-
b)
a)
; ODT Signal: FLOATING
a)
; AL: 0; CS: High between REF;
; AL: 0; CS, Command,
H5TQ4G43MMR-xxC
H5TQ4G83MMR-xxC
a)
a)
; AL: 0; CS, Command,
; AL: 0; CS, Command,
e)
e)
; CKE:
40
;
e)
;