h5tq4g43mmr Hynix Semiconductor, h5tq4g43mmr Datasheet - Page 41

• Manufacturer Part Number: h5tq4g43mmr
• Description: 4gb Ddr3 Sdram Ddp
• Manufacturer: Hynix Semiconductor

Rev. 0.1 /Aug 2008
a) Burst Length: BL8 fixed by MRS: set MR0 A[1,0]=00B
b) Output Buffer Enable: set MR1 A[12] = 0B; set MR1 A[5,1] = 01B; RTT_Nom enable: set MR1 A[9,6,2] = 011B;
RTT_Wr enable: set MR2 A[10,9] = 10B
c) Precharge Power Down Mode: set MR0 A12=0B for Slow Exit or MR0 A12 = 1B for Fast Exit
d) Auto Self-Refresh (ASR): set MR2 A6 = 0B to disable or 1B to enable feature
e) Self-Refresh Temperature Range (SRT): set MR2 A7 = 0B for normal or 1B for extended temperature range
f) Refer to DRAM supplier data sheet and/or DIMM SPD to determine if optional features or requirements are supported by
DDR3 SDRAM device
Table 3 - IDD0 Measurement-Loop Pattern
a) DM must be driven LOW all the time. DQS, DQS are FLOATING.
b) DQ signals are FLOATING.
I
DD7
Operating Bank Interleave Read Current
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, NRRD, nFAW, CL: see Table 1 on page 38; BL: 8
AL: CL-1; CS: High between ACT and RDA; Command, Address, Bank Address Inputs: partially toggling
according to Table 10 on page 46; Data IO: read data burst with different data between one burst and the next
one according to Table 10 on page 46; DM: stable at 0; Bank Activity: two times interleaved cycling through
banks (0, 1,...7) with different addressing, wee Table 10 on page 46; Output Buffer and RTT: Enabled in Mode
Registers
0
1
2
3
4
5
6
7
0
1,2
3,4
...
nRAS
...
1*nRC+0
...
1*nRC+nRAS
...
2*nRC
4*nRC
6*nRC
8*nRC
10*nRC
12*nRC
14*nRC
b)
; ODT Signal: stable at 0; Pattern Details: see Table 10 on page 46
repeat pattern 1...4 until nRAS - 1, truncate if necessary
repeat pattern 1...4 until nRC - 1, truncate if necessary
repeat pattern 1...4 until 1*nRC + nRAS - 1, truncate if necessary
repeat pattern 1...4 until 2*nRC - 1, truncate if necessary
repeat Sub-Loop 0, use BA[2:0] = 1 instead
repeat Sub-Loop 0, use BA[2:0] = 2 instead
repeat Sub-Loop 0, use BA[2:0] = 3 instead
repeat Sub-Loop 0, use BA[2:0] = 4 instead
repeat Sub-Loop 0, use BA[2:0] = 5 instead
repeat Sub-Loop 0, use BA[2:0] = 6 instead
repeat Sub-Loop 0, use BA[2:0] = 7 instead
PRE
PRE
ACT
D, D
D, D
ACT
0
1
1
0
0
0
a)
0
0
1
0
0
0
1
0
1
1
1
1
1
0
1
0
1
0
0
0
0
0
0
0
00
0
0
0
0
0
00
00
00
00
00
00
0
0
0
0
0
0
0
0
0
0
0
0
H5TQ4G43MMR-xxC
H5TQ4G83MMR-xxC
F
F
0
0
0
0
0
0
0
0
0
0
Data
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-
-
-
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41
b)
a)
;