h5tq4g43mmr Hynix Semiconductor, h5tq4g43mmr Datasheet - Page 3
h5tq4g43mmr
Manufacturer Part Number
h5tq4g43mmr
Description
4gb Ddr3 Sdram Ddp
Manufacturer
Hynix Semiconductor
Datasheet
1.H5TQ4G43MMR.pdf
(73 pages)
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Rev. 0.1 /Aug 2008
1. Description
2. Command Description
3. Absolute Maximum Ratings
4. Operating Conditions
5. AC and DC Input Measurement Levels
1.1 Device Features and Ordering Information
1.2 Package Ball out
1.3 Row and Column Address Table: 512M/1G Fixed
1.4 Pin Functional Description
1.5 Functional Block Diagram
2.1 Command Truth Table
2.2 Clock Enable (CKE) Truth Table for Synchronous Transitions
4.1 Operating Temperature Condition
4.2 DC Operating Conditions
5.1 AC and DC Logic Input Levels for Single-Ended Signals
5.2 AC and DC Logic Input Levels for Differential Signals
5.3 Differential Input Cross Point Voltage
5.4 Slew Rate Definitions for Single Ended Input Signals
5.5 Slew Rate Definitions for Differential Input Signals
1.1.1 Description
1.1.2 Features
1.1.3 Ordering Information
1.1.4 Ordering Frequency
5.4.1 Input Slew Rate for Input Setup Time (tIS) and Data Setup Time (tDS)
5.4.2 Input Slew Rate for Input Hold Time (tIH) and Data Hold Time (tDH)
Table of Contents
H5TQ4G43MMR-xxC
H5TQ4G83MMR-xxC
3
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