h5tq4g43mmr Hynix Semiconductor, h5tq4g43mmr Datasheet - Page 32

• Manufacturer Part Number: h5tq4g43mmr
• Description: 4gb Ddr3 Sdram Ddp
• Manufacturer: Hynix Semiconductor

Rev. 0.1 /Aug 2008
7.6 ODT Timing Definitions
7.6.1 Test Load for ODT Timings
Different than for timing measurements, the reference load for ODT timings is defined in Figure .
7.6.2 ODT Timing Reference Load
ODT Timing Definitions
Definitions for tAON, tAONPD, tAOF, tAOFPD and tADC are provided in the table and subsequent figures. Measurement
reference settings are provided in the table.
ODT Timing Definitions
Reference Settings for ODT Timing Measurements
Symbol
t
t
AONPD
AOFPD
t
t
t
AON
AOF
ADC
CK,
Parameter
Measured
t
t
AONPD
AOFPD
CK
t
t
t
AON
AOF
ADC
Rising edge of CK - CK defined by the end point of
Timing Reference Points
ODTLcnw, ODTLcwn4 or ODTLcwn8
DUT
Rising edge of CK - CK defined by
Rising edge of CK - CK defined by
ODT being first registered high
ODT being first registered low
Rising edge of CK - CK with
Rising edge of CK - CK with
RTT_Nom Setting
the end point of ODTLon
the end point of ODTLoff
Begin Point Definition
VDDQ
VSSQ
DQ, DM
DQS,
TDQS,
R
R
R
R
R
R
R
R
R
ZQ
ZQ
ZQ
ZQ
ZQ
ZQ
ZQ
ZQ
ZQ
DQS
/12
/12
/12
/12
/12
TDQS
/4
/4
/4
/4
RTT_Wr Setting
= 25 Ω
RTT
R
BD_REFLOAD_ODT
NA
NA
NA
NA
NA
NA
NA
NA
ZQ
/2
VTT =
VSSQ
End point: Extrapolated point at VRTT_Wr and
End point: Extrapolated point at VRTT_Nom
End point: Extrapolated point at VRTT_Nom
V
SW1
Extrapolated point at VSSQ
Extrapolated point at VSSQ
0.05
0.10
0.05
0.10
0.05
0.10
0.05
0.10
0.20
VRTT_Nom respectively
End Point Definition
[V]
V
SW2
H5TQ4G43MMR-xxC
H5TQ4G83MMR-xxC
0.10
0.20
0.10
0.20
0.10
0.20
0.10
0.20
0.30
[V]
Note
Figure
Figure
Figure
Figure
Figure
Figure
32