cn8236 Mindspeed Technologies, cn8236 Datasheet - Page 175

• Manufacturer Part Number: cn8236
• Description: Atm Servicesar Plus With Xbr Traffic Management
• Manufacturer: Mindspeed Technologies

CN8236
ATM ServiceSAR Plus with xBR Traffic Management
6.2.1 Scheduling Priority
6.2.2 Dynamic Schedule Table
28236-DSH-001-B
6.2.1.2 VCC Priority
6.2.1.1 16 Priority
6.2.2.1 Overview
Levels + CBR
Assignment
6.2 xBR Cell Scheduler Functional Description
The CN8236 supports 16 scheduling priorities (the PRI field in the SEG VCC
table entry), in addition to the optional CBR service category, with 15 being the
highest priority, down to 0 being the lowest priority. CBR channels are assigned a
priority which is in effect higher than the 16 scheduling priorities discussed here.
From one to 16 of these scheduling priorities can be assigned to VBR and ABR
service classes. The others are shared UBR priorities. The VBR/ABR priorities
must be contiguous within the 16 scheduling priorities, and thus accessible by an
offset pointer. The host sets the offset of the VBR/ABR priorities in the
VBR_OFFSET field of SEG_CTRL or SCH_CTRL.
The host assigns the priority of all VCCs, except CBR VCCs, by setting the PRI
field in the Segmentation VCC table entry. This priority should be set at
connection setup and should not be changed dynamically.
The xBR Cell Scheduler schedules traffic according to the Dynamic Schedule
table. The table contains a programmable number of slots, determined by
SCH_SIZE(TBL_SIZE). The duration of a single slot is a programmable number
of clocks cycles, set as the number of clock cycles per schedule slot, in
SCH_SIZE(SLOT_PER). The Cell Scheduler sequences through this table in a
circular fashion to schedule CBR, VBR, and ABR traffic. UBR traffic is handled
as described in
of each slot, the system designer chooses a range of available rates. This range of
available rates is dictated by the rate at which a single slot is scheduled, the size of
the table, and how many slots in the Dynamic Schedule table each channel is
assigned.
register, as shown in
Table 6-2. Scheduler Clock Selection
The scheduler clock is selected by bit 26 (USE_SCHREF) of the SCH_CTRL
USE_SCHREF
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Table
6.2.5. By configuring the number of slots and the duration
6-2.
Scheduler Clock
SYSCLK
SCHREF
™
6.2 xBR Cell Scheduler Functional Description
6.0 Traffic Management
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