cn8236 Mindspeed Technologies, cn8236 Datasheet - Page 385

• Manufacturer Part Number: cn8236
• Description: Atm Servicesar Plus With Xbr Traffic Management
• Manufacturer: Mindspeed Technologies

CN8236
ATM ServiceSAR Plus with xBR Traffic Management
16.1.4 CN8236 Memory Interface Timing
Table 16-5. SRAM Organization Loading Dependencies
Table 16-6. SAR Shared Memory Output Loading Conditions
28236-DSH-001-B
LADDR[18:0]
LDATA[31:0]
MWR*
MOE*
MCSx*
MWEx*
NOTE(S):
(1)
(2)
LADDR[18:0]
MOE*
MWR*
LDATA[31:0]
MWE[3:0]*
MCS[3:0]*
NOTE(S):
(1)
(2)
In general, the LADDR loading is the most critical parameter. One bank of by_8 SRAM has the same address loading as two
banks of by_16 and 1/2 bank of by_4 SRAM. For example, use the timing from the two banks of by_8 column for four banks
of by_16 SRAM, or one bank of by_4 SRAM.
For by_16 SRAM, the WE* input has the same loading as the address bus and OE*; therefore, 16 loads specified by the four
banks of by_8 is not applicable, since the maximum number of by_16 SRAMs supported is eight.
Typical input loading for SRAM is 7 pF. For exact values, consult the SRAM databook.
Only connected to one bank by definition.
(1)
(1)
(2)
(1, 2)
(1)
Signal
Signal
(1)
(1)
(1)
Memory access times and other timing requirements are specified at three typical
implementations of one, two, and four banks of by_8 SRAM.
number of loads per bank for the different SRAM organizations, while
lists the capacitive loading used in the timing specifications given for the three
typical implementations. CN8236 memory interface timing is provided in
Table
4 banks of by_8
16-7. (See
by_16 SRAM
SRAM
150
150
Mindspeed Technologies
—
50
50
50
2
1
2
2
2
1
Memory Interface Loading
Section
9.2, for details of memory bank organization.)
2 banks of by_8
SRAM
100
100
50
35
35
35
Loads/Bank
by_8 SRAM
16.0 Electrical and Mechanical Specifications
(1)
N/A
4
1
4
4
1
™
(1)
by_8 SRAM
1 bank of
50
50
35
25
25
25
Table 16-5
by_4 SRAM
N/A
8
1
8
8
2
Table 16-6
16.1 Timing
Units
lists the
pF
pF
pF
pF
pF
pF
16-9