cn8236 Mindspeed Technologies, cn8236 Datasheet - Page 345

• Manufacturer Part Number: cn8236
• Description: Atm Servicesar Plus With Xbr Traffic Management
• Manufacturer: Mindspeed Technologies

CN8236
ATM ServiceSAR Plus with xBR Traffic Management
14.6.1 Host Interrupt Status Registers
These two registers contain all interruptible status bits for the host processor. The corresponding interrupt
enables are located in the HOST_IMASKx registers. Status types are defined as follows:
28236-DSH-001-B
DE
L
E
Mindspeed Technologies
NOTE:
Level-sensitive status—A logic 1 on the status bit causes an interrupt
when enabled by the corresponding IMASK bit. Reading the status
does not clear the status or interrupt. The source of the condition
causing the status must be cleared before the status or interrupt is
cleared.
Event driven status—A 0 > 1 transition on the status bit causes an
interrupt when enabled. Reading the status register clears the status bit
and the interrupt.
Dual Event status—A 0 > 1 and 1 > 0 transition on the status bit can
be enabled to cause an interrupt. Reading the status register clears the
status bit and the interrupt.
Only host reads reset the status bits in the HOST_ISTAT0
register.
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14.6 Counters and Status Registers
14.0 CN8236 Registers
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