cn8236 Mindspeed Technologies, cn8236 Datasheet - Page 311

• Manufacturer Part Number: cn8236
• Description: Atm Servicesar Plus With Xbr Traffic Management
• Manufacturer: Mindspeed Technologies

28236-DSH-001-B
13.0 AALx Interworking
The AALx is a programmable platform that supports development of various
voice processing algorithms. Header processing is required since the cells from
various channels are streamed to or from one FIFO buffer in the AALx. The
function of the SAR is to integrate AALx and Host Processor traffic (that is,
management) and to provide traffic shaping in network centric scheduling
applications. This solution supports up to six AALx parts.
mailbox registers. In order for the SAR to communicate with the AALx FIFO
buffer, the RSM and SEG need to be configured in 52-octet logical FIFO buffer
mode, and the FIFO buffer on the AALx must be in slave access mode. On the
ingress side, the RSM block performs ATM header lookup on each cell and steers
the voice data cells to the appropriate AALx. In addition, it determines the state
of the AALx ingress FIFO buffer and drop cells if full.
centric scheduling and voice centric scheduling. In network centric scheduling,
the scheduling table can be locked to the network cell rate. CBR entries are
written for each AALx. When a transmit opportunity is detected, the SEG block
determines the state of the appropriate AALx egress FIFO buffer and retrieves a
cell if available. In voice centric scheduling, the SEG block constantly determines
the state of each AALx egress FIFO buffer and retrieves and transmits a cell as
soon as one is available.
better support network-centric scheduling, an external scheduler reference clock
is supplied. In addition, the PHYs add a cell slot reference output clock. In order
for the RSM to determine the state of the AALx ingress FIFO buffer, the AALx
toggles a GPIO output every time it reads a cell from the FIFO buffer. This output
is connected to the HFIFORDx input of the SAR. The RSM block maintains a
shadow FIFO buffer read counter and can determine if there is room to accept
another cell. Similarly, the AALx toggles another GPIO output every time it
writes a cell to the egress FIFO buffer. This output is connected to the
HFIFOWRx input. The SEG maintains a shadow FIFO buffer write counter to
determine that a cell is available. The ingress and egress FIFO buffer shadow
counters have a programmable FIFO buffer depth up to 16 cells via the
AALx_CTRL register.
PCI Masters communicate with AALxs through either a FIFO buffer or
On the egress side, the SEG block supports two scheduling modes, network
The transmission of a cell bumps management cells scheduled by the SAR. To
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