cn8236 Mindspeed Technologies, cn8236 Datasheet - Page 303

• Manufacturer Part Number: cn8236
• Description: Atm Servicesar Plus With Xbr Traffic Management
• Manufacturer: Mindspeed Technologies

CN8236
ATM ServiceSAR Plus with xBR Traffic Management
Figure 12-3. Transmit Timing in UTOPIA Level 1 Mode with Cell Handshake
28236-DSH-001-B
TXD/TXPAR
NOTE(S):
(1)
(2)
(3)
(4)
TXCLAV
TXSOC
TXCLK
Once transfer of a cell is started, TxClav is sampled only on the last octet of a cell.
TxEN* goes active if TxClav is inactive at previous rising clock edge and a complete cell in the transmit FIFO buffer.
TxEN* goes inactive due to TxClav being active on previous cycle.
TxEN* goes inactive since a complete cell is not in the transmit FIFO buffer.
TXEN*
(2)
H1
***
TxEN* is asserted. TxEN* is only asserted when there is data in the CN8236
transmit FIFO buffer. Simultaneously, the odd parity computed over the
TxData[15:0] lines is driven on to the TxPar output. The TxSOC line is driven by
the framer device to indicate start of cell. If the TxCLAV input is asserted by the
framer device, the framer device is full, and another cell is not transmitted to the
physical framer. (See
output; a 50% duty cycle clock derived by dividing CLK2X by three.
Transmit data is driven on TxData[15:0] on the rising edge of TxClk when
In UTOPIA mode, the TxClk input can be connected to the CN8236 CLKD3
P44
Mindspeed Technologies
P45
P46
Figure
P47
12-3.)
P48
(1)
12.5 UTOPIA Level 1 Mode Cell Handshake Timing
™
X
(3)
H1
12.0 ATM UTOPIA Interface
***
P48
(4)
X
12-13
8236_072