cn8236 Mindspeed Technologies, cn8236 Datasheet - Page 63

• Manufacturer Part Number: cn8236
• Description: Atm Servicesar Plus With Xbr Traffic Management
• Manufacturer: Mindspeed Technologies

CN8236
ATM ServiceSAR Plus with xBR Traffic Management
Table 2-1. Hardware Signal Definitions (1 of 6)
28236-DSH-001-B
HAD[31:0]
HC/BE[3:0]*
HPAR
HFRAME*
HIRDY*
HTRDY*
HSTOP*
HDEVSEL*
HIDSEL
HREQ*
HGNT*
HINT*
Pin Label
Multiplexed
Address/Data Bus
Command/Byte Enable
Address/Data
Command Parity
Transaction Initiator
Ready
Transaction Target
Ready
Transaction Termination
Bus Device
Acknowledge
Interrupt Request
Bus Grant
Framing Signal
Bus Device Slot Select
Arbiter Bus Request
Signal Name
Mindspeed Technologies
I/O
OD
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
I
I
Used by the PCI host or CN8236 to transfer addresses or data
over the PCI bus.
Outputs a command (during PCI address phases) or byte
enables (during data phases) for each bus transaction.
Supplies the even parity computed over the HAD[31:0] and
HC/BE[3:0]* lines during valid data phases. It is sampled
(when the CN8236 is acting as a target) or driven (when the
CN8236 acts as an initiator) one clock edge after the
respective data phase.
A high-to-low HFRAME* transition indicates that a new
transaction is beginning (with an address phase). A
low-to-high transition indicates that the next valid data phase
ends the current transaction.
Used by the transaction initiator or bus master (either the
CN8236 or the PCI host) to indicate ready for data transfer. A
valid data transfer occurs when both HIRDY* and HTRDY* are
active on the same clock edge.
Used by the transaction target or bus slave (either the CN8236
or the PCI bus memory) to indicate that it is ready for a data
transfer. A valid data transfer occurs when both HIRDY* and
HTRDY* are active on the same clock edge.
Driven by the current target or slave (either the CN8236 or the
PCI bus memory) to abort, disconnect, or retry the current
transfer. The HSTOP* line is used by the PCI master in
conjunction with the HTRDY* and HDEVSEL* lines to
determine the type of transaction termination.
Driven by a target to indicate to the initiator that the address
placed on the HAD[31:0] lines (together with the command on
the HC/BE[3:0]* lines) has been decoded and accepted as a
valid reference to the target’s address space. Once asserted, it
is held by the CN8236 (when acting as a slave) until HFRAME*
is deasserted; otherwise, it indicates (in conjunction with
HSTOP* and HTRDY*) a target abort.
Signals the CN8236 that it is being selected for a configuration
space access.
Asserted by the CN8236 to request control of the PCI bus.
Asserted to indicate to the CN8236 that it has been granted
control of the PCI bus, and can begin driving the address/data
and control lines after the current transaction has ended
(indicated by HFRAME*, HIRDY*, and HTRDY*; all deasserted
simultaneously).
Signals an interrupt request to the PCI host, and is tied to the
INTA_ line on the PCI bus.
™
2.10 Logic Diagram and Pin Descriptions
Definition
2.0 Architecture Overview
2-29