cn8236 Mindspeed Technologies, cn8236 Datasheet - Page 51

• Manufacturer Part Number: cn8236
• Description: Atm Servicesar Plus With Xbr Traffic Management
• Manufacturer: Mindspeed Technologies

CN8236
ATM ServiceSAR Plus with xBR Traffic Management
Figure 2-9. Multi-Level Model for Prioritizing Segmentation Traffic
28236-DSH-001-B
NOTE(S):
Host
(1)
(2)
(3)
(4)
(5)
The user initializes traffic parameters on a per-VCC basis.
User selects priority or round-robin service policy on transmit queues.
The segmentation coprocessor notifies the Traffic Manager when a VCC becomes active, through
reading new entries from the transmit queue.
Each conforming non-CBR VCC is assigned to a priority queue, while conforming CBR VCCs
are simply slated for transmit.
The highest priority conforming cell is formatted and put on the Tx FIFO buffer for transmit.
Buffers
Data
Parameters
Transmit Queues
(1)
Traffic
Control
Tables
VCC
(32)
actually maintained on a per-transmit opportunity basis. In this way, high
priority traffic is transmitted up to its GCRA limits but does not block
lower priority traffic when idle. The CN8236 asynchronously multiplexes
traffic based on the above schemes as the Tx FIFO buffer empties.
Mindspeed Technologies
Figure 2-9
(2)
Start
Templates
Schedule
Table
ABR
(3)
shows this prioritization as a global set of queues, but it is
Segmentation
Coprocessor
xBR Traffic
Manager
Conforming
VCC ID #
16 UBR/VBR/ABR
Priority Queues
Next Tx VCC ID #
SAR
(5)
™
CBR
2.5 Advanced xBR Traffic Management
Full/Empty
(4)
UBR/VBR/ABR
VCC ID #
Tx FIFO
2.0 Architecture Overview
Buffer
To
PHY
8236_009
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