IDT82V3380AEQGBLANK IDT [Integrated Device Technology], IDT82V3380AEQGBLANK Datasheet - Page 122

• Manufacturer Part Number: IDT82V3380AEQGBLANK
• Manufacturer: IDT [Integrated Device Technology]

T4_INPUT_SEL_CNFG - T4 Selected Input Clock Configuration
Programming Information
IDT82V3380A
Address: 51H
Type: Read / Write
Default Value: X0000000
3 - 0
Bit
7
6
5
4
7
-
T4_INPUT_SEL[3:0]
T4_TEST_T0_PH
T4_LOCK_T0
T4_LOCK_T0
T0_FOR_T4
Name
6
-
Reserved.
This bit determines whether the T4 DPLL locks to a T0 DPLL output or locks independently from the T0 DPLL.
0: Independently from the T0 path. (default)
1: Locks to a 77.76 MHz or 8 kHz signal from the T0 DPLL 77.76 MHz path.
This bit is valid only when the T4_LOCK_T0 bit (b6, 51H) is ‘1’. It determines whether a 77.76 MHz or 8 kHz signal from the
T0 DPLL 77.76 MHz path is selected by the T4 DPLL.
0: 77.76 MHz. (default)
1: 8 kHz.
This bit determines whether T4 selected input clock is compared with the feedback signal of the T4 DPLL for T4 DPLL locking
or is compared with the T0 selected input clock to get the phase difference between T0 and T4 selected input clocks.
0: The T4 DPLL output. (default)
1: The T0 selected input clock.
These bits are valid only when the T4_LOCK_T0 bit (b6, 51H) is ‘0’. They determines the T4 DPLL input clock selection.
0000: Automatic selection. (default)
0001: Forced selection - IN1 is selected.
0010: Forced selection - IN2 is selected.
......
1101: Forced selection - IN13 is selected.
1110: Forced selection - IN14 is selected.
1111: Reserved.
T0_FOR_T4
5
T4_TEST_T0_PH
4
122
T4_INPUT_SEL3
3
Description
T4_INPUT_SEL2
2
SYNCHRONOUS ETHERNET WAN PLL™
T4_INPUT_SEL1
1
T4_INPUT_SEL0
May 16, 2011
0