IDT82V3380AEQGBLANK IDT [Integrated Device Technology], IDT82V3380AEQGBLANK Datasheet - Page 15

• Manufacturer Part Number: IDT82V3380AEQGBLANK
• Manufacturer: IDT [Integrated Device Technology]

Pin Description
IDT82V3380A
Table 1: Pin Description (Continued)
MPU_MODE0
MPU_MODE1
MPU_MODE2
OUT6_POS
OUT6_NEG
OUT7_POS
OUT7_NEG
OUT8_POS
OUT8_NEG
INT_REQ
Name
OUT3
OUT4
OUT5
OUT9
CS
Pin No.
I/O
90
93
94
34
35
36
37
28
27
95
60
59
58
8
pull-down
pull-up
I/O
O
O
O
O
O
O
O
O
I
I
PECL/LVDS
PECL/LVDS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
Type
AMI
OUT3: Output Clock 3
A 1 Hz, 400 Hz, 2 kHz, 8 kHz, 64 kHz, N x E1
10 MHz, 20 MHz, 25 MHz, E3, T3, 6.48 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz,
77.76 MHz, 125 MHz, 155.52 MHz, 156.25 MHz or 312.5 MHz clock is output on this pin.
OUT4: Output Clock 4
A 1 Hz, 400 Hz, 2 kHz, 8 kHz, 64 kHz, N x E1
10 MHz, 20 MHz, E3, T3, 6.48 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz
or 155.52 MHz clock is output on this pin.
OUT5: Output Clock 5
A 1 Hz, 400 Hz, 2 kHz, 8 kHz, 64 kHz, N x E1
10 MHz, 20 MHz, E3, T3, 6.48 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz
or 155.52 MHz clock is output on this pin.
OUT6_POS / OUT6_NEG: Positive / Negative Output Clock 6
A 1 Hz, 400 Hz, 2 kHz, 8 kHz, 64 kHz, N x E1
10 MHz, 20 MHz, E3, T3, 6.48 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz,
155.52 MHz, 311.04 MHz or 622.08 MHz clock is differentially output on this pair of pins.
OUT7_POS / OUT7_NEG: Positive / Negative Output Clock 7
A 1 Hz, 400 Hz, 2 kHz, 8 kHz, 64 kHz, N x E1
10 MHz, 20 MHz, 25 MHz, E3, T3, 6.48 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz,
77.76 MHz, 125 MHz, 155.52 MHz, 156.25 MHz, 311.04 MHz, 312.5 MHz or 622.08 MHz clock is
differentially output on this pair of pins.
OUT8_POS / OUT8_NEG: Positive / Negative Output Clock 8
A 64 kHz + 8 kHz or 64 kHz + 8 kHz + 0.4 kHz composite clock is differentially output on this pair
of pins.
OUT9: Output Clock 9
A 1.544 MHz (SONET) / 2.048 MHz (SDH) BITS/SSU clock is output on this pin.
CS: Chip Selection
In EPROM mode, this pin is an output. In Multiplexed, Intel, Motorola and Serial modes, this pin is
an input. A transition from high to low must occur on this pin for each read or write operation and
this pin should remain low until the operation is over.
INT_REQ: Interrupt Request
This pin is used as an interrupt request. The output characteristics are determined by the HZ_EN
bit (b1, 0CH) and the INT_POL bit (b0, 0CH).
MPU_MODE[2:0]: Microprocessor Interface Mode Selection
The device supports five microprocessor interface modes: EPROM, Multiplexed, Intel, Motorola
and Serial.
During reset, these pins determine the default value of the MPU_SEL_CNFG[2:0] bits (b2~0, 7FH)
as follows:
001 (EPROM mode);
010 (Multiplexed mode);
011 (Intel mode);
100 (Motorola mode);
101 (Serial mode);
110 - 111 (Reserved).
After reset, these pins are general purpose inputs. The microprocessor interface mode is selected
by the MPU_SEL_CNFG[2:0] bits (b2~0, 7FH).
After reset de-assertion, wait 10 µs for the mode to be active.
The value of these pins is always reflected by the MPU_PIN_STS[2:0] bits (b2~0, 02H).
Microprocessor Interface
15
Description
4
4
4
4
4
SYNCHRONOUS ETHERNET WAN PLL™
, N x T1
, N x T1
, N x T1
, N x T1
, N x T1
1
5
5
5
5
5
, N x 13.0 MHz
, N x 13.0 MHz
, N x 13.0 MHz
, N x 13.0 MHz
, N x 13.0 MHz
6
6
6
6
6
, N x 3.84 MHz
, N x 3.84 MHz
, N x 3.84 MHz
, N x 3.84 MHz
, N x 3.84 MHz
May 16, 2011
7
7
7
7
7
, 5 MHz,
, 5 MHz,
, 5 MHz,
, 5 MHz,
, 5 MHz,