IDT82V3380AEQGBLANK IDT [Integrated Device Technology], IDT82V3380AEQGBLANK Datasheet - Page 73

• Manufacturer Part Number: IDT82V3380AEQGBLANK
• Manufacturer: IDT [Integrated Device Technology]

DIFFERENTIAL_IN_OUT_OSCI_CNFG - Differential Input / Output Port & Master Clock Configuration
Programming Information
IDT82V3380A
Address: 0AH
Type: Read / Write
Default Value: XXXXX001
7 - 3
Bit
2
1
0
7
-
OUT7_PECL_LVDS
OUT6_PECL_LVDS
OSC_EDGE
Name
-
6
-
Reserved.
This bit selects a better active edge of the master clock.
0: The rising edge. (default)
1: The falling edge.
This bit selects a port technology for OUT7.
0: LVDS. (default)
1: PECL.
This bit selects a port technology for OUT6.
0: LVDS.
1: PECL. (default)
5
-
4
-
73
3
-
Description
OSC_EDGE
2
SYNCHRONOUS ETHERNET WAN PLL™
OUT7_PECL_LVDS
1
OUT6_PECL_LVDS
May 16, 2011
0