IDT82V3380AEQGBLANK IDT [Integrated Device Technology], IDT82V3380AEQGBLANK Datasheet - Page 147

• Manufacturer Part Number: IDT82V3380AEQGBLANK
• Manufacturer: IDT [Integrated Device Technology]

OUT9_FREQ_CNFG - Output Clock 9 Frequency Configuration & Output Clock 1 ~ 5 Invert Configuration
Programming Information
IDT82V3380A
Address:73H
Type: Read / Write
Default Value: 01000000
OUT9_PATH_S
Bit
7
6
5
4
3
2
1
0
EL
7
OUT9_PATH_SEL
T4_INPUT_FAIL
OUT5_INV
OUT4_INV
OUT3_INV
OUT2_INV
OUT1_INV
OUT9_EN
Name
OUT9_EN
6
These bits select an input to OUT9.
0: The output of T4 DPLL 16E1/16T1 path. (default)
1: The output of T0 DPLL 16E1/16T1 path.
Refer to the description of the T4_INPUT_FAIL bit (b5, 73H).
This bit, together with the OUT9_EN bit (b6, 73H), determines whether clock is enabled to output on OUT9.
This bit determines whether the output on OUT5 is inverted.
0: Not inverted. (default)
1: Inverted.
This bit determines whether the output on OUT4 is inverted.
0: Not inverted. (default)
1: Inverted.
This bit determines whether the output on OUT3 is inverted.
0: Not inverted. (default)
1: Inverted.
This bit determines whether the output on OUT2 is inverted.
0: Not inverted. (default)
1: Inverted.
This bit determines whether the output on OUT1 is inverted.
0: Not inverted. (default)
1: Inverted.
T4_INPUT_FAI
OUT9_EN
0
1
5
L
T4_INPUT_FAIL
don’t-care
OUT5_INV
0
1
4
input clock does not change to be invalid, the T4 selected input clock does not fail).
(Whether the T4 selected input clock is switched or not, as long as the T4 selected
147
Output is disabled (output low) when the T4 selected input clock fails.
OUT4_INV
Output is enabled when the T4 selected input clock does not fail.
3
Description
Output is disabled (output low).
Output is enabled. (default)
OUT3_INV
Output on OUT9
2
SYNCHRONOUS ETHERNET WAN PLL™
OUT2_INV
1
OUT1_INV
May 16, 2011
0