IDT82V3380AEQGBLANK IDT [Integrated Device Technology], IDT82V3380AEQGBLANK Datasheet - Page 59

• Manufacturer Part Number: IDT82V3380AEQGBLANK
• Manufacturer: IDT [Integrated Device Technology]

Table 43: Read Timing Characteristics in Serial Mode
5.5
When CLKE is asserted low, data on SDO will be clocked out on the ris-
Microprocessor Interface
IDT82V3380A
In a read operation, the active edge of SCLK is selected by CLKE.
Symbol
t
t
t
t
t
pw1
pw2
t
t
t
t
t
su1
su2
t
out
T
d1
d2
h1
h2
TI
in
SERIAL MODE
SCLK
SDI
SDO
SDO
CS
SCLK
SDI
Time between consecutive Read-Read or Read-Write accesses
CS
CS rising edge to SDO high impedance delay time
Valid CS after valid SCLK hold time (CLKE = 0/1)
t
t
su2
su1
R/W
R/W
Valid SDI after valid SCLK hold time
Valid SCLK to valid data delay time
Valid SDI to valid SCLK setup time
(CS rising edge to CS falling edge)
One cycle time of the master clock
Valid CS to valid SCLK setup time
t
Figure 26. Serial Read Timing Diagram (CLKE Asserted High)
Figure 25. Serial Read Timing Diagram (CLKE Asserted Low)
h1
A0
SCLK pulse width high
SCLK pulse width low
A0
Delay of output pad
Delay of input pad
Parameter
A1
A1
A2
High-Z
A2
High-Z
t
pw1
A3
A3
t
pw2
A4
A4
A5
A5
59
A6
A6
ing edge of SCLK. When CLKE is asserted high, data on SDO will be
clocked out on the falling edge of SCLK.
of SCLK.
t
d1
In a write operation, data on SDI will be clocked in on the rising edge
t
d1
D0
D0
5T + 10
5T + 10
Min
14
10
4
6
5
D1
D1
D2
D2
D3
SYNCHRONOUS ETHERNET WAN PLL™
D3
12.86
Typ
10
10
5
5
D4
D4
D5
D5
D6
D6
t
d2
Max
t
h2
t
D7
t
d2
D7
h2
May 16, 2011
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns