or3l165b Lattice Semiconductor Corp., or3l165b Datasheet - Page 17

• Manufacturer Part Number: or3l165b
• Description: Orca Or3lxxxb Series Field-programmable Gate Arrays
• Manufacturer: Lattice Semiconductor Corp.

Data Addendum
March 2002
Lattice Semiconductor
Timing Characteristics
Table 8. Synchronous Memory Write Characteristics
OR3LxxB Commercial: V
to 3.6 V, V
* The RAM is written on the inactive clock edge following the active edge that latches the address, data, and control signals.
Note: The table shows worst-case delays. ORCA Foundry reports the delays for individual paths within a group of paths representing the same
Write Operation for RAM Mode
Write Operation Setup Time
Write Operation Hold Time
SMCLKH_MPW
SMCLKL_MPW
CIN, DIN[7, 5, 3, 1]
SMCLK_FRQ
WPE0_SET
WPE1_SET
WPE0_HLD
WPE1_HLD
MEM_DEL
WA4_SET
WA4_HLD
timing parameter and may accurately report delays that are less than those listed.
ASWE (WREN)
WD_SET
WD_HLD
WE_HLD
WA_SET
WE_SET
WA_HLD
Symbol
DIN[6, 4, 2, 0]
CE (WPE0),
LSR(WPE1)
F[6, 4, 2, 0]
DD
2 = 2.38 V to 2.63 V, –40 °C
CK
SMCLKH_MPW
Maximum Frequency
Clock Low Time
Clock High Time
Clock to Data Valid (CLK to F[6, 4, 2, 0])*
Address to Clock (CIN to CLK)
Address to Clock (DIN[7, 5, 3, 1] to CLK)
Data to Clock (DIN[6, 4, 2, 0] to CLK)
Write Enable (WREN) to Clock (ASWE to CLK)
Write-port Enable 0 (WPE0) to Clock (CE to CLK)
Write-port Enable 1 (WPE1) to Clock (LSR to CLK)
Address from Clock (CIN from CLK)
Address from Clock (DIN[7, 5, 3, 1] from CLK)
Data from Clock (DIN[6, 4, 2, 0] from CLK)
Write Enable (WREN) from Clock (ASWE from CLK)
Write-port Enable 0 (WPE0) from Clock (CE from CLK)
Write-port Enable 1 (WPE1) from Clock (LSR from CLK)
DD
= 3.0 V to 3.6 V, V
Figure 4. Synchronous Memory Write Characteristics
WPE0_SET
WPE1_SET
(continued)
WE_SET
<
T
A
Parameter
DD
<
WA4_SET
WA_SET
WD_SET
+85 °C.
2 = 2.38 V to 2.63 V, 0 °C
WA4_HLD
WA_HLD
WD_HLD
WE_HLD
WPE0_HLD
WPE1_HLD
ORCA OR3LxxxB Series FPGAs
<
T
A
MEM_DEL
<
1.03
1.96
0.68
0.35
0.21
0.37
0.87
1.10
0.33
Min
70 °C; Industrial: V
0.0
0.0
0.0
0.0
0.0
—
—
-7
SMCLKL_MPW
266.4
Max
4.39
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0.90
1.71
0.59
0.30
0.18
0.32
0.75
0.95
0.29
Min
0.0
0.0
0.0
0.0
0.0
—
—
-8
DD
333.0
Max
3.82
—
—
—
—
—
—
—
—
—
—
—
—
—
—
= 3.0 V
5-4621 (F)b
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
17