or3l165b Lattice Semiconductor Corp., or3l165b Datasheet - Page 29

• Manufacturer Part Number: or3l165b
• Description: Orca Or3lxxxb Series Field-programmable Gate Arrays
• Manufacturer: Lattice Semiconductor Corp.

Data Addendum
March 2002
Lattice Semiconductor
Timing Characteristics
Table 18. OR3Lxxx General System Clock (SCLK) to Output Delay (Pin-to-Pin)
OR3LxxB Commercial: V
to 3.6 V, V
Note: This clock delay is for a fully routed clock tree that uses the primary clock network. It includes both the input
Output On Same Side of Device As Input Clock (System Clock Delays Using General
User I/O Inputs)
Clock Input Pin (mid-PIC) →OUTPUT Pin
(Fast)
Clock Input Pin (mid-PIC) →OUTPUT Pin
(Slewlim)
Clock Input Pin (mid-PIC) →OUTPUT Pin
(Sinklim)
Additional Delay if Non-mid-PIC Used as
Clock Pin
Output Not on Same Side of Device As Input Clock (System Clock Delays Using
General User I/O Inputs)
Additional Delay if Output Not on Same
Side as Input Clock Pin
(T
buffer delay, the clock routing to the PIO CLK input, the clock→Q of the FF, and the delay through the output
buffer. The delay will be reduced if any of the clock branches are not used. The given timing requires that the
input clock pin be located at one of the four center PICs on any side of the device and that a PIO FF be used.
For clock pins located at any other PIO, see the results reported by ORCA Foundry.
J
= 85 °C, V
DD
2 = 2.38 V to 2.63 V, –40 °C
Description
DD
= min, V
DD
= 3.0 V to 3.6 V, V
DD
SCLK
2 = min)
(continued)
Figure 8. System Clock to Output Delay
<
T
A
OR3L165
OR3L225
OR3L165
OR3L225
OR3L165
OR3L225
OR3L165
OR3L225
OR3L165
OR3L225
DD
<
Device
+85 °C.
2 = 2.38 V to 2.63 V, 0 °C
D
PIOFF
Q
Min
—
—
—
—
—
—
—
—
—
—
-7
OUTPUT (50 pF LOAD)
11.81
12.32
12.66
13.16
17.78
18.28
Max
1.04
1.43
1.04
1.43
ORCA OR3LxxxB Series FPGAs
<
Min
—
—
—
—
—
—
—
—
—
—
T
A
<
-8
70 °C; Industrial: V
10.06
10.54
11.85
11.34
15.29
15.78
Max
1.03
1.43
1.03
1.43
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DD
= 3.0 V
5-4846(F)
29