or3l165b Lattice Semiconductor Corp., or3l165b Datasheet - Page 33

• Manufacturer Part Number: or3l165b
• Description: Orca Or3lxxxb Series Field-programmable Gate Arrays
• Manufacturer: Lattice Semiconductor Corp.

Data Addendum
March 2002
Lattice Semiconductor
Timing Characteristics
Table 20. OR3Lxxx Input to Fast Clock Setup/Hold Time (Pin-to-Pin) (continued)
OR3LxxB Commercial: V
to 3.6 V, V
Notes:
The pin-to-pin timing parameters in this table should be used instead of results reported by ORCA Foundry.
The FCLK delays are for a fully routed clock tree that uses the ExpressCLK input into the fast clock network.
It includes both the input buffer delay and the clock routing to the PFU CLK input. The delay will be reduced
if any of the clock branches are not used.
Input to FCLK Hold Time
(middle ECLK pin, delayed data input)
Input to FCLK Hold Time
(corner ECLK pin)
Input to FCLK Hold Time
(corner ECLK pin, delayed data input)
(T
J
= 85 °C, V
DD
2 = 2.38 V to 2.63 V, –40 °C
Description
DD
= min, V
DD
DD
= 3.0 V to 3.6 V, V
2 = min)
Figure 10. Input to Fast Clock Setup/Hold Time
(continued)
INPUT
ECLK
<
OR3L165
OR3L225
OR3L165
OR3L225
OR3L165
OR3L225
Device
T
A
DD
<
+85 °C.
2 = 2.38 V to 2.63 V, 0 °C
7.59
8.08
CLKCNTRL
Min
0.0
0.0
0.0
0.0
-7
FCLK
Max
—
—
—
—
—
—
D
PIO FF
6.61
7.06
Min
0.0
0.0
0.0
0.0
ORCA OR3LxxxB Series FPGAs
Q
-8
<
T
Max
A
—
—
—
—
—
—
<
70 °C; Industrial: V
Unit
ns
ns
ns
ns
ns
ns
DD
= 3.0 V
5-4847(F).a
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