or3l165b Lattice Semiconductor Corp., or3l165b Datasheet - Page 8

• Manufacturer Part Number: or3l165b
• Description: Orca Or3lxxxb Series Field-programmable Gate Arrays
• Manufacturer: Lattice Semiconductor Corp.

ORCA OR3LxxxB Series FPGAs
Description
PIC Logic
The OR3LxxxB PIC addresses the demand for ever-
increasing system clock speeds. Each PIC contains
four programmable inputs/outputs (PIOs) and routing
resources. On the input side, each PIO contains a fast-
capture latch that is clocked by an ExpressCLK. This
latch is followed by a latch/FF that is clocked by a sys-
tem clock from the internal general clock routing. The
combination provides for very low setup requirements
and zero hold times for signals coming on-chip. It may
also be used to demultiplex an input signal, such as a
multiplexed address/data signal, and register the sig-
nals without explicitly building a demultiplexer. Two
input signals are available to the PLC array from each
PIO, and the ORCA Series 2 capability to use any input
pin as a clock or other global input is maintained.
8 8
OUT1
OUT2
ECLK
SCLK
LSR
CE
ENABLE_GSR
DISABLE_GSR
0
1
Figure 3. OR3Lxxx Programmable Input/Output Image from ORCA Foundry
(continued)
0
0
CE_OVER_LSR
LSR_OVER_CE
ASYNC
AND
NAND
OR
NOR
XOR
XNOR
OUT1OUTREG
OUT2OUTREG
OUT1OUT2
PIO LOGIC
PMUX
D
CK
SP
LSR
Q
RESET
SET
TS
D0 Q
CK
LSR
1
BUFFER
MODE
FAST
SLEW
SINK
PULL-MODE
LEVEL MODE
On the output side of each PIO, two outputs from the
PLC array can be routed to each output flip-flop, and
logic can be associated with each I/O pad. The output
logic associated with each pad allows for multiplexing
of output signals and other functions of two output sig-
nals.
The output FF, in combination with output signal multi-
plexing, is particularly useful for registering address
signals to be multiplexed with data, allowing a full clock
cycle for the data to propagate to the output. The I/O
buffer associated with each pad is very similar to the
Series 2 buffer with a new, fast, open-drain option for
ease of use on system buses. These features may also
be combined with the new 3-state FF that allows the
3-state control signal to be registered. This allows for
early control setup and faster clock-to-out times.
UP
DOWN
NONE
PAD
TTL
CMOS
PD
SCLK
ECLK
1
INREGMODE
NORMAL
INVERTED
LATCHFF
LATCH
FF
D
CK
Q
Lattice Semiconductor
Data Addendum
RESET
SET
D0
D1
CK
SP
SD
LSR
Q
March 2002
CLKIN
IN1
IN2
5-5805(F).a