or3l165b Lattice Semiconductor Corp., or3l165b Datasheet - Page 21

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or3l165b

Manufacturer Part Number
or3l165b
Description
Orca Or3lxxxb Series Field-programmable Gate Arrays
Manufacturer
Lattice Semiconductor Corp.
Datasheet

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Data Addendum
March 2002
Lattice Semiconductor
Timing Characteristics
Table 12. Programmable I/O Timing Characteristics (continued)
OR3LxxB Commercial: V
to 3.6 V, V
Note: The delays for all input buffers assume an input rise/fall time of <1 V/ns
Output Delays (T
OUTGSRSL_DEL
OUTREGSL_DEL
OUTLSRSL_DEL
OUTGSRSI_DEL
OUTREGSI_DEL
OUTLSRSI_DEL
OUTGSRF_DEL
OUTREGF_DEL
OUTLSRF_DEL
OUTLSR_SET
OUTLSR_HLD
OUTCE_HLD
OUTCE_SET
OUTSL_DEL
OUTSI_DEL
OUTE_SET
OUTE_HLD
OUTF_DEL
TSSL_DEL
TSSI_DEL
OUT_HLD
OUT_SET
TSF_DEL
OD_DEL
Symbol
DD
2 = 2.38 V to 2.63 V, –40 °C
J
= 85 °C, V
Output to Pad (OUT2, OUT1 direct to pad):
3-state Enable/Disable Delay (TS to pad):
Local Set/Reset (async) to Pad (LSR to pad):
Global Set/Reset to Pad (GSRN to pad):
Output FF Setup Timing:
Output FF Hold Timing:
Clock to Pad Delay (ECLK, SCLK to pad):
Additional Delay If Using Open Drain
Fast
Slewlim
Sinklim
Fast
Slewlim
Sinklim
Fast
Slewlim
Sinklim
Fast
Slewlim
Sinklim
Out to ExpressCLK (OUT[2:1] to ECLK)
Out to Clock (OUT[2:1] to CLK)
Clock Enable to Clock (CE to CLK)
Local Set/Reset (sync) to Clock (LSR to CLK)
Out from ExpressCLK (OUT[2:1] from ECLK)
Out from Clock (OUT[2:1] from CLK)
Clock Enable from Clock (CE from CLK)
Local Set/Reset (sync) from Clock (LSR from CLK)
Fast
Slewlim
Sinklim
DD
= 3.0 V to 3.6 V, V
DD
(continued)
= min, C
Parameter
<
L
T
= 50 pF)
A
DD
<
+85 °C.
2 = 2.38 V to 2.63 V, 0 °C
ORCA OR3LxxxB Series FPGAs
0.44
0.05
0.32
0.32
<
Min
0.0
0.0
0.0
0.0
T
A
-7
<
10.14
10.24
12.09
10.60
11.05
Max
3.79
4.71
3.86
4.66
5.70
6.58
5.05
5.75
4.67
5.55
0.11
70 °C; Industrial: V
0.39
0.04
0.28
0.28
Min
0.0
0.0
0.0
0.0
-8
10.52
10.43
Max
3.21
3.91
8.84
3.29
3.99
8.92
4.90
5.60
4.81
5.51
4.02
4.72
9.64
0.09
DD
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
= 3.0 V
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